On Thu, 31 Aug 2006 08:46:19 +0200
Juan RP <juan@xtrarom.org> wrote:

> On Tue, 29 Aug 2006 22:03:50 +1000
> Simon Burge <simonb@NetBSD.org> wrote:
> 
> > and sysctl says:
> > 
> >   machdep.est.frequency.target = 1000
> >   machdep.est.frequency.current = 1000
> >   machdep.est.frequency.available = 1833 1000
> > 
> > It defaulted to 1830 MHz, and I've since changed it 1000 MHz.  The
> > lmbench "mhz" program says the frequencies appear to be correct.
>  
> Good news, Simon made a patch that will create a fake table with all values
> (not only highest and lowest) using an algorithm:
> 
> http://www.xtrarom.org/~juan/juan-est-plus-fake-table.diff
> 
> I tried it on my Pentium M 745 1800MHz and it did show 13 frequencies.
> The known table for this CPU only has 6 freqs, so I thought the algorithm
> wasn't working correctly, but I think it's working fine because openssl
> speed seems to ok.
> 
> dmesg with this patch: http://www.xtrarom.org/~juan/new_est-1.dmesg
> 
> And tests made with openssl speed:
> 
> http://www.xtrarom.org/~juan/new_est_tests.txt
> 
> Could you please test this patch on NetBSD if you have a SpeedStep
> capable CPU and report results of all frequencies running openssl speed
> (only first three values is enough).

Changing line 1003 to:

voltinc = voltinc * 100 / freqinc - 1;

Seems to match the lowest entry:

 cpu0: Enhanced SpeedStep (1340 mV) 1800 MHz
cpu0: unknown Enhanced SpeedStep CPU.
est_init: bus_clock = 10000
est_init: idlo = 0x612
est_init: lo   988 mV,  600 MHz
est_init: raw   18   ,    6    
est_init: idhi = 0x1228
est_init: hi  1340 mV, 1800 MHz
est_init: raw   40   ,   18    
est_init: cur  = 0x1228
est_init: fake entry 0: 1340 mV, 1800 MHz  MSR*100 mV = 1800 freq = 4000
est_init: fake entry 1: 1324 mV, 1700 MHz  MSR*100 mV = 1700 freq = 3816
est_init: fake entry 2: 1292 mV, 1600 MHz  MSR*100 mV = 1600 freq = 3632
est_init: fake entry 3: 1260 mV, 1500 MHz  MSR*100 mV = 1500 freq = 3448
est_init: fake entry 4: 1228 mV, 1400 MHz  MSR*100 mV = 1400 freq = 3264
est_init: fake entry 5: 1196 mV, 1300 MHz  MSR*100 mV = 1300 freq = 3080
est_init: fake entry 6: 1164 mV, 1200 MHz  MSR*100 mV = 1200 freq = 2896
est_init: fake entry 7: 1148 mV, 1100 MHz  MSR*100 mV = 1100 freq = 2712
est_init: fake entry 8: 1116 mV, 1000 MHz  MSR*100 mV = 1000 freq = 2528
est_init: fake entry 9: 1084 mV,  900 MHz  MSR*100 mV =  900 freq = 2344
est_init: fake entry 10: 1052 mV,  800 MHz  MSR*100 mV =  800 freq = 2160
est_init: fake entry 11: 1020 mV,  700 MHz  MSR*100 mV =  700 freq = 1976
est_init: fake entry 12:  988 mV,  600 MHz  MSR*100 mV =  600 freq = 1792
cpu0: Enhanced SpeedStep frequencies available (MHz): 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600