juan@xtrarom.org (Juan RP) writes:

>Anybody could please review it before committing? at least this version
>of est.c will detect the highest and lowest frequency in CPUs that we
>don't know the table and will work in more CPUs than before.

On a T2300 it works somewhat. I have to run sysctl several times
to get the speed changed. I guess the speed needs to be set on
both cores indvidually.

dmesg shows:

cpu0: features2 c1a9<SSE3,MONITOR,VMX,EST,TM2,xTPR>
cpu1: features2 c1a9<SSE3,MONITOR,VMX,EST,TM2,xTPR>

cpu0: Enhanced SpeedStep (1404 mV) 1667 MHz
cpu0: unknown Enhanced SpeedStep CPU.
cpu0: Enhanced SpeedStep frequencies available (MHz): 1667 1500 1333 1167 1000
cpu1: Enhanced SpeedStep (1404 mV) 1667 MHz
cpu1: Enhanced SpeedStep frequencies available (MHz): 1667 1500 1333 1167 1000

When I retry sysctl often enough so that it reports the same frequency
that I wanted to set then the result is ok. A quick 'openssl speed blowfish'
confirms the setting:

          16 bytes     64 bytes    256 bytes   1024 bytes   8192 bytes
1000MHz  30226.23k    32502.54k    33400.65k    33561.57k    33661.92k
1167MHz  35090.05k    37684.77k    38728.61k    38911.99k    39028.55k
1333MHz  40130.22k    43067.92k    44264.05k    44476.24k    44610.55k
1500MHz  45422.93k    48753.11k    50103.48k    50343.07k    50495.66k
1667MHz  50307.58k    54170.96k    55671.52k    55937.34k    56106.92k


-- 
-- 
                                Michael van Elst
Internet: mlelstv@serpens.de
                                "A potential Snark may lurk in every tree."