David Laight wrote:
> On Mon, Sep 04, 2006 at 01:35:02PM -0700, Garrett D'Amore wrote:
>   
>> Masking interrupts doesn't work on very high end SMP hardware.  You're
>> still trying to design for systems with less than 8 CPUs.
>>     
>
> You only need to mask it on the current cpu.
> Which is all spl() has to do.
>   

Huh?  If I have user code entering the driver on processor 1, and the
interrupt is being handled on processor 2, then I had better make sure
that _somehow_ the data integrity is retained.  Simply masking
interrupts on processor 1 isn't going to help processor 2.

Unless you mask interrupts on _all_ processors.  Or force a processor in
an ISR on another CPU to spin on the lock?

I think Solaris' answer to this is to prevent drivers from normally
using locks that are 'high level', unless they are willing to special
action to limit their use.  Normal devices (including, e.g. all PCI
devices) have ISRs that run on a thread that can just use ordinary locks
-- i.e. the Solaris framework manages the splx() at interrupt dispatch
time, and the driver code never directly causes it to be changed. 
(Ignoring "high level interrupts", for which I suspect Solaris just
makes the ISR spin.)

In any case, this is an _implementation detail_.  Driver developers
shouldn't be thinking about processor interrupt levels.  They should be
thinking about protecting their data structures or device access.

-- 
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134  Fax: 951 325-2191