Re: IPLs - One too many?

[Rafal Boni <rafal%pobox.com@localhost>]

On Thu, Jul 24, 2008 at 03:21:04PM -0700, Matt Thomas wrote:
> 
> I've been talking to Chris Gilbert for a while about eliminating nested
> interrupts in one or more of the ARM ports.
> 
> Ignoring IPL_SOFT* IPLs for the moment, ARM currently has
> IPL_NONE < IPL_VM < IPL_SCHED < IPL_HIGH
> 
> Since IPL_SCHED == IPL_CLOCK, once IPL_SCHED is reached you block
> clock interrupts.  Since clock interrupts are the highest priority
> interrupts, you have basically blocked all interrupts.  So there
> is little difference between IPL_HIGH and IPL_SCHED.
> 
> So why have both?  Can I just make IPL_HIGH == IPL_SCHED?
> 
> This means I have three IPL value, IPL_NONE, IPL_VM, IPL_HIGH.
> 
> And now I can directly map those to the ARM CPSR bits IF32_bits
> (IRQ, FIQ) as 00, 10, 11 so I can make IPL_NONE=0, IPL_VM=2, and
> IPL_HIGH=3 and have no reason to store a s/w copy of the IPL since
> the CPU status word will contain an encoding of it.

Yes, please!  I think this would be a very good thing, given how ugly
and pervasive the code to handle global-IRQ-disable is and the subtle
differences in platform code that handles the details of setting up
the interrupt state so we can do nested interrupts.

The only thing I can think of that could be a wrinkle here is whether
this would get us low enough latency to deal with high-speed serial
interrupts -- esp. for e.g. UART-connected BlueTooth interfaces.

--rafal

-- 
  Time is an illusion; lunchtime, doubly so.     |/\/\|           Rafal Boni
                   -- Ford Prefect               |\/\/|      
rafal%pobox.com@localhost