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Re: EHCI of SoC
Hi! all,
I make re-new patch.
I will commit next weekend.
Thanks,
--
kiyohara
Index: ehci.c
===================================================================
RCS file: /cvsroot/src/sys/dev/usb/ehci.c,v
retrieving revision 1.169
diff -u -r1.169 ehci.c
--- ehci.c 7 Jul 2010 03:55:01 -0000 1.169
+++ ehci.c 8 Oct 2010 11:06:58 -0000
@@ -392,6 +392,8 @@
aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev));
return (USBD_IOERROR);
}
+ if (sc->sc_vendor_init)
+ sc->sc_vendor_init(sc);
/* XXX need proper intr scheduling */
sc->sc_rand = 96;
@@ -2260,6 +2262,8 @@
if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET;
+ if (sc->sc_vendor_port_status)
+ i = sc->sc_vendor_port_status(sc, v, i);
USETW(ps.wPortChange, i);
l = min(len, sizeof ps);
memcpy(buf, &ps, l);
@@ -2289,7 +2293,7 @@
case UHF_PORT_RESET:
DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
index));
- if (EHCI_PS_IS_LOWSPEED(v)) {
+ if (EHCI_PS_IS_LOWSPEED(v) && sc->sc_ncomp > 0) {
/* Low speed device, give up ownership. */
ehci_disown(sc, index, 1);
break;
@@ -2304,7 +2308,8 @@
goto ret;
}
/* Terminate reset sequence. */
- EOWRITE4(sc, port, v);
+ v = EOREAD4(sc, port);
+ EOWRITE4(sc, port, v & ~EHCI_PS_PR);
/* Wait for HC to complete reset. */
usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
if (sc->sc_dying) {
Index: ehcivar.h
===================================================================
RCS file: /cvsroot/src/sys/dev/usb/ehcivar.h,v
retrieving revision 1.36
diff -u -r1.36 ehcivar.h
--- ehcivar.h 24 Feb 2010 22:38:09 -0000 1.36
+++ ehcivar.h 8 Oct 2010 11:06:59 -0000
@@ -167,6 +167,9 @@
device_t sc_child; /* /dev/usb# device */
char sc_dying;
struct usb_dma_reserve sc_dma_reserve;
+
+ void (*sc_vendor_init)(struct ehci_softc *);
+ int (*sc_vendor_port_status)(struct ehci_softc *, uint32_t, int);
} ehci_softc_t;
#define EREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (a))
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