Hello,
I'm going to add MSI/MSI-X support to NetBSD. I list tasks about this.
Would you comment following task list?
TODO
basic idea: keep current implementation as we can.
+ [x86 common MD] separate status of interrupt handlers to "registered" and
"assigned"
- currently, registering interrupt handler and assigning CPU are done at
a time in pci_intr_establish().
- If there are more than one CPUs and they handle multiple interrupts include
MSI/MSI-X, it is difficult to manage them.
+ [x86 common MD] increase the max number of registered interrupt handlers
- currently, the number of supported interrupts is
(32 (MAX_INTR_SOURCES - 7 (for softint)) * number of CPUs
- increase this number, for example, up to 768 (like FreeBSD)
- include 512 for MSI/MSI-X.
+ [x86 common MD] implement intr_establish() for MSI
- enhance intr_establish() fpr MSI or add a new function.
- register interrupt handlers.
- separate it from assigning CPUs.
+ [MI] implement MI API for MSI
- not yet determined
- Where should MSI's address and data be set?
- in struct device? (like FreeBSD)
- One of the way is to use API like FreeBSD to make device driver's
portability well.
+ [x86 common MD] implement MD intr_establish() for MSI-X
- enhance intr_establish() for MSI or add a new function.
+ [MI] implement MI API for MSI-X
- different API from MSI
- because device drivers treat MSI and MSI-X in a different way
- generally MSI uses only one interrupt vector.
- MSI-X uses multi interrupt vecotrs, futhermore multi interrupt handlers.
FUTURE WORK
+ [amd64 MD] modify callers of INTRSTUB
- unifying ioapic_edge and ioapic_level should be done with spl rearrangement
- unifying legacy may be needed too?
+ [amd64 MD] refactor INTRSTUB
- currently, it walks the interrupt handler list in assembly code
- I want to use NetBSD's list library, so I want to convert this assembly
code to C code.
+ [amd64 MD] increase the max number of assigned interrupt handlers
- currently, the number of supported interrupt is
(32 (MAX_INTR_SOURCES - 7 (for softint))
- increase this number to 64 (max bit length which amd64 can manipulate
atomically) like OpenBSD.
- hopefully, increase this number to
0xef (IDT_INTR_HIGH) - 0x20 (IDT entries for exception) + "number of
softints"
- this modification needs expanding struct cpu_info.ipending to
a length more than 64bit (which cannot manipulate atomically),
so it's required to protect ipending with mutex(9).
but muntex_spin_exit() uses ipending...
- furthermore, increase related arrays and flags.
+ [x86 common MD] separate Interrupt Descriptor Table (IDT) for each CPU
- this is needed to manipulate interrupts over the number of one CPU's
IDT entries.
- DragonflyBSD maybe implements this.
+ [x86 common MD] implement a new struct to manipulate local APIC
- this struct may be needed when one interrupt is assigned to multi CPUs
aka "logical destination mode".
--
//////////////////////////////////////////////////////////////////////
Internet Initiative Japan Inc.
Device Engineering Section,
Core Product Development Department,
Product Division
Kengo NAKAHARA <k-nakahara%iij.ad.jp@localhost>