Re: Understanding SPL(9)

[Manuel Bouyer <bouyer%antioche.eu.org@localhost>]

On Mon, Aug 31, 2015 at 01:06:53PM +0200, Stephan wrote:
> Hi!
> 
> I´m trying to understand interrupt priority levels using the example
> of x86. From what I´ve seen so far I´d say that all spl*() functions
> end up in either splraise() or spllower() from
> sys/arch/i386/i386/spl.S. What these functions actually do is not
> clear to me. For example, splraise() starts with this:
> 
> ENTRY(splraise)
>         movl    4(%esp),%edx
>         movl    CPUVAR(ILEVEL),%eax
>         cmpl    %edx,%eax
>         ja      1f
>         movl    %edx,CPUVAR(ILEVEL)
> ...
> 
> I´m unable to find out what CPUVAR(ILEVEL) means.

it's curcpu()->ci_ilevel (the ci_ilevel value for the current cpu).

> I would guess that
> something needs to happen to the APIC´s task priority register.

No, it does not. when an interrupt vector is entered, it compares
the spl level of each interrupt handler registered for this vector
against curcpu()->ci_ilevel. If the spl of the handler is higher it's called
directly, otherwise it's deffered until a splx() call lowers ci_ilevel
enough.

-- 
Manuel Bouyer <bouyer%antioche.eu.org@localhost>
     NetBSD: 26 ans d'experience feront toujours la difference
--