Re: Understanding SPL(9)

[Eduardo Horvath <eeh%NetBSD.org@localhost>]

On Mon, 31 Aug 2015, Stephan wrote:

> I´m trying to understand interrupt priority levels using the example
> of x86. From what I´ve seen so far I´d say that all spl*() functions
> end up in either splraise() or spllower() from
> sys/arch/i386/i386/spl.S. What these functions actually do is not
> clear to me. For example, splraise() starts with this:
> 
> ENTRY(splraise)
>         movl    4(%esp),%edx
>         movl    CPUVAR(ILEVEL),%eax
>         cmpl    %edx,%eax
>         ja      1f
>         movl    %edx,CPUVAR(ILEVEL)
> ...
> 
> I´m unable to find out what CPUVAR(ILEVEL) means. I would guess that
> something needs to happen to the APIC´s task priority register.
> However I can´t see any coherence just now.

Don't look at x86, it doesn't have real interrupt levels.  Look at SPARC 
or 68K which do.

Most machines nowadays only have one interrupt line and an external 
interrupt controller.  True interrupt levels are simulated by assigning 
levels to individual interrupt sources and masking the appropriate ones in 
the interrupt controller.  This makes the code rather complicated, 
especially since interrupts can nest.

If you want to see cleaner implementations look at machines with hardware 
interrupt levels.

Eduardo