Re: amd64: svs

[Maxime Villard <max%m00nbsd.net@localhost>]

Le 11/01/2018 à 20:14, Jaromír Doleček a écrit :
> 2018-01-10 19:56 GMT+01:00 Maxime Villard <max%m00nbsd.net@localhost <mailto:max%m00nbsd.net@localhost>>:
>  > That's what we do, too. Doing this is faster than "unmapping the kernel pages
>  > on return to user space".
>  >
>  > Switching the address space costs one "movq %rax,%cr3".
>
> Yes, but address space switch also causes an implicit TLB/paging structure
> cache flush when not using something like PCID, doesn't it?

yes

>  >> Do you reckon SVS has potential of having lower overall overhead than
>  >> separate address spaces + PCID? Alternatively, do you think SVS would benefit
>  >> if we added PCID support to x86 pmap?
>  >
>  > Yes, it would benefit if we added PCID.
>
> Okay, I'll look into this. The feature seems pretty simple to use, though it will need
> some care to allow inactive processes to relinguish PCID when there is shortage.
> I'll try to not disturb your SVS work.
>
>  > Probably, but there are still many CPUs without PCID out there, and for them
>  > a blunt separation will unfortunately still be needed.
>
> Haswell and later have it. Latest benchmarks for Linux and Windows confirm
> the performance impact of their sw mitigations is significantly higher on CPUs
> without PCID, so it's all the more important to have this too.

Yes, now that meltdown is out, it's important to have PCID. In SVS I'm only
doing the general case - that is, switching entirely and flushing the cache.
If you want to implement PCID, you are welcome.

Maxime