Re: Intel 82801H SATA interrupt issues

["Jonathan A. Kollasch" <jakllsch%kollasch.net@localhost>]

On Thu, Sep 05, 2024 at 12:53:00AM +0000, Emmanuel Dreyfus wrote:
> On Wed, Sep 04, 2024 at 06:17:31AM +0000, Emmanuel Dreyfus wrote:
> > I gave it a try by patching ahci match routine, but got no success so far.
> 
> In ahci_pci_match I tried this:
> 
> 	pcireg_t v;
> 	const int ich89_address_map_reg = 0x90;
> 
> 	v = pci_conf_read(pa->pa_pc, pa->pa_tag, ich89_address_map_reg);
> 	printf("armval = 0x%08x\n", v);
> 
> 	v |= 0x40;
> 	v &= ~0x80;
> 	printf("write back armval = 0x%08x\n", v);
> 	pci_conf_write(pa->pa_pc, pa->pa_tag, ich89_address_map_reg, v);
> 
> 	v = pci_conf_read(pa->pa_pc, pa->pa_tag, ich89_address_map_reg);
> 	printf("updated armval = 0x%08x\n", v);
> 
> Result:
> [   1.0041382] armval = 0x01030000
> [   1.0041382] write back armval = 0x01030040
> [   1.0041382] updated armval = 0x01030000
> 
> Is there something I am doing obviously wrong? I note the documentation
> says only the BIOS should do this, but how is this different from the 
> BIOS doing it? The controller is not yet in operation.

Some of these bits can either be write once or can be otherwise locked
by platform firmware.  Not sure that's applicable to these bits, but
it's a possibility.