Re: What if the console device is only accessible from one CPU in a multiprocessor system?

[Mouse <mouse%Rodents-Montreal.ORG@localhost>]

> So, DEC made a class of machines, â??Laserâ?? (and later, â??TurboLaserâ??) $

> The purpose of this message is to spur a discussion about how to handle this$

This reminds me of a multiprocessor MicroVAX-II.  While most devices
are on the Qbus and can be poked from any processor, each processor's
`console' SLU is accessible from only that processor - it's the console
serial ports that particularly remind me of what you outline here.  (On
the uV2, RAM is also asymmetric; each processor has its own RAM, and,
while it can be (usually partially) exported over the Qbus, it is
significantly slower to access RAM a different processor is exporting
than it is to access local RAM.  Also, most device interrupts go to
only the arbiter processor.)

I'd say the *right* thing to do is to treat this as a special case of
something more general, of peripherals which can be accessed by only
certain cores.  (I'm not sure whether it's worth the complexity of the
full generality of each device being restricted to a subset of cores
rather than a single core.)

Of course, from me, this is armchair quarterbacking, since I won't be
doing the work and won't even be using the result.  But it _is_ another
example of something that already showed up decades ago (the uV2 dates
from...the mid-'80s, I think, certainly pre-1990), and it seems to me
it is unlikely to be the last example.

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