On Mon, Mar 04, 2002 at 08:56:54AM -0800, Jason R Thorpe wrote:

 > Yes.  The errors you are getting are indicitave of a saturated PCI bus
 > (a Tx underrun happens when the PCI can't keep the Tx FIFO fed as fast
 > as the MAC can drain it).  Once the underruns climb up to a certain point,
 > do they stop happening?

To follow up... you might try tweaking the Latency Timer PCI config
register.  This defines the "timeslice" that the device gets.  The BIOS
is supposed to set this according to the device's MIN_GNT register, but
if you have a lot of devices on the bus that all want a big timeslice,
the configuration software might not have done quite what you want.

Try increasing the LT value in for the device in the BIOS config menus
(the value is in units of PCI clocks, and the bottom 3 bits are usually
always 0, i.e. you can generally change it with a granularity of 8 clocks).

-- 
        -- Jason R. Thorpe <thorpej@wasabisystems.com>