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On Friday 16 January 2004 9:34 pm, Andrew Kilpatrick wrote:

> I saw some changes to the vr0 code so I moved from 1.6.1 to 1.6.2_RC3
> but am still have troubles.

Can you apply the attached patch to sys/dev/pci/if_vr.c, and try again? 
The patch is relative to -current, but will apply cleanly to 1.6.2_RC3.

Cheers, Steve

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Index: if_vr.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_vr.c,v
retrieving revision 1.65
retrieving revision 1.67
diff -u -r1.65 -r1.67
--- if_vr.c	17 Oct 2003 17:42:35 -0000	1.65
+++ if_vr.c	14 Nov 2003 22:33:29 -0000	1.67
@@ -1563,9 +1563,22 @@
 	 * they've been programmed a special way. Consequently,
 	 * we need to read the node address from the PAR0 and PAR1
 	 * registers.
-	 */
-	VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
-	DELAY(200);
+	 *
+	 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload
+	 *         of the *whole* EEPROM, not just the MAC address. This is
+	 *         pretty pointless since the chip does this automatically
+	 *         at powerup/reset.
+	 *         I suspect the same thing applies to the other Rhine
+	 *         variants, but in the absence of a data sheet for those
+	 *         (and the lack of anyone else noticing the problems this
+	 *         causes) I'm going to retain the old behaviour for the
+	 *         other parts.
+	 */
+	if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 &&
+	    PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102) {
+		VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
+		DELAY(200);
+	}
 	for (i = 0; i < ETHER_ADDR_LEN; i++)
 		eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
 

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