Fixing Yukon EC Ultra power up issue

[Chris Gilbert <chris%dokein.co.uk@localhost>]

Hi,

Attached is a patch for if_msk.c to fix a power-on issue where the phys
don't respond on a cold boot, so the server hangs probing phys.

Without the patch I have to PXE boot the server (so the NIC BIOS warms
up the phys) and then boot netbsd.

It's based on the code from FreeBSD:
http://www.freebsd.org/cgi/cvsweb.cgi/src/sys/dev/msk/if_msk.c?rev=1.34;content-type=text%2Fx-cvsweb-markup
specifically the function msk_phy_power.

From what I can tell it's just making sure that some extra EC-Ultra
registers are in a known state.

I've also taken the liberty of adding an splnet/splx across mii_tick().
 This seems to be common to most other NIC drivers.

Any objections to me checking the attached patch in?  Ideally I'd like
to do so by the end of the weekend.

Actually ideally I'd like to use the FreeBSD driver, it seems more
readable (with some functions broken up into smaller parts) than our
current driver or the OpenBSD driver, but I don't have the time to do
the porting work.

Actually I also noticed that FreeBSD seems to have a phy driver for the
phy as well.  I seem to be using ukphy.

Thanks,
Chris

Index: if_msk.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_msk.c,v
retrieving revision 1.21
diff -u -p -r1.21 if_msk.c
--- if_msk.c    20 Jun 2008 16:45:13 -0000      1.21
+++ if_msk.c    3 Oct 2008 14:26:20 -0000
@@ -808,6 +808,26 @@ void msk_reset(struct sk_softc *sc)
                reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
        else
                reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
+       
+       if (sc->sk_type == SK_YUKON_EC_U) {
+               uint32_t our;
+
+               CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON);
+               
+               /* enable all clocks. */
+               sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0);
+               our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4));
+               our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST|
+                       SK_Y2_REG4_ASPM_GPHY_LINK_DOWN|
+                       SK_Y2_REG4_ASPM_INT_FIFO_EMPTY|
+                       SK_Y2_REG4_ASPM_CLKRUN_REQUEST);
+               /* Set all bits to 0 except bits 15..12 */ 
+               sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our);
+               /* Set to default value */
+               sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0);
+       }
+
+       /* release PHY from PowerDown/Coma mode. */
        sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
  
        if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
@@ -1803,8 +1823,12 @@ msk_tick(void *xsc_if)
 {
        struct sk_if_softc *sc_if = xsc_if;  
        struct mii_data *mii = &sc_if->sk_mii;
+       int s;
 
+       s = splnet();
        mii_tick(mii);
+       splx(s);
+
        callout_schedule(&sc_if->sk_tick_ch, hz);
 }
 
Index: if_skreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_skreg.h,v
retrieving revision 1.12
diff -u -p -r1.12 if_skreg.h
--- if_skreg.h  28 Apr 2008 20:23:55 -0000      1.12
+++ if_skreg.h  3 Oct 2008 14:26:22 -0000
@@ -204,6 +204,8 @@
 #define SK_CSR_BUSCLOCK                        0x0200 /* 1 == 33/66 MHz, = 33 
*/
 #define SK_CSR_ASF_OFF                 0x1000
 #define SK_CSR_ASF_ON                  0x2000
+#define SK_CSR_WOL_OFF                 __BIT(14)
+#define SK_CSR_WOL_ON                  __BIT(15)
 
 /* SK_LED register */
 #define SK_LED_GREEN_OFF               0x01
@@ -1504,10 +1506,25 @@
 #define SK_PCI_VPD_NEXTPTR     0x0051
 #define SK_PCI_VPD_ADDR                0x0052
 #define SK_PCI_VPD_DATA                0x0054
+#define SK_PCI_OURREG3         0x0080 /* Yukon EC U */
+#define SK_PCI_OURREG4         0x0084
+#define SK_PCI_OURREG5         0x0088
 
 #define SK_Y2_REG1_PHY1_COMA   0x10000000
 #define SK_Y2_REG1_PHY2_COMA   0x20000000
 
+/* SK_PCI_OURREG4 32bits (Yukon-ECU only) */
+#define SK_Y2_REG4_TIMER_VALUE_MSK     (0xff << 16)
+#define SK_Y2_REG4_FORCE_ASPM_REQUEST  __BIT(15)       
+#define SK_Y2_REG4_ASPM_GPHY_LINK_DOWN __BIT(14)
+#define SK_Y2_REG4_ASPM_INT_FIFO_EMPTY __BIT(13)
+#define SK_Y2_REG4_ASPM_CLKRUN_REQUEST __BIT(12)
+#define SK_Y2_REG4_ASPM_FORCE_CLKREQ_ENA       __BIT(4)
+#define SK_Y2_REG4_ASPM_CLKREQ_PAD     __BIT(3)
+#define SK_Y2_REG4_ASPM_A1_MODE_SELECT __BIT(2)
+#define SK_Y2_REG4_CLK_GATE_PEX_UNIT_ENA       __BIT(1)
+#define SK_Y2_REG4_CLK_GATE_ROOT_COR_ENA       __BIT(0)
+
 #define SK_PSTATE_MASK         0x0003
 #define SK_PSTATE_D0           0x0000
 #define SK_PSTATE_D1           0x0001