Re: tlp(4) DMA synchronization

[Thor Lancelot Simon <tls%panix.com@localhost>]

On Sat, Aug 29, 2009 at 03:53:54AM +0900, Izumi Tsutsui wrote:
> 
> On mips, the cacheline size can be 128 bytes, while most systems
> use 32 bytes. Wasting 128 byte DMA safe memory for 16 byte descs
> might be problematic on some ports, because such memory could be
> limited resource and bus_dmamem_alloc(9) might fail for too large
> segments, especially on attaching devices on running systems which
> could have less physically contiguous memory than at boot time.

The effective cache line size on some i386 and amd64 systems can be
128 bytes, because the cache lines are 64 bytes but adjacent cache
line prefetch means fetching one fetches two.  I believe the snoopy
logic still uses a 64 byte granularity though.

-- 
Thor Lancelot Simon                                        
tls%rek.tjls.com@localhost
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