On Mon, 15 Apr 2002, Mike O'Brien wrote:

> On Fri, Apr 12, 2002 at 11:35:39AM -0700, Byan, Stephen wrote:
> > BTW, the PDP-11/20 and PDP-11/40 didn't have memory mappers; that was an
> > option for the PDP-11/45.

> 	If I recall correctly, the 11/20 did not have a memory
> mapper, nor segment registers either; it was a flat-address-space
> machine.  I might be wrong about the segment registers, because
> I never worked with one, but this is what I recall (the 11/20 was
> the first PDP-11).

Sorry for generating more noise on this topic, but since I own an 11/34,
11/45 and three 11/70s, and worked for DEC in the 70s let me set the record
straight.

The 11/20 did not have segmentation registers.  It could address 56 KB of
memory, as the upper 8K bytes were reserved for peripheral addresses.  It
did have an 18-bit unibus, but memory references where A15=A14=A13=1 also
forced A17 and A16 to 1.


The pdp-11/40 had memory management available as the KT11-D Memory
Management option, and the KJ11-A Stack Limit option.  The KT11-D allowed
greater than 28 KW of memory, protection, and relocation.

There were two special registers, the Page Address Register (PAR), and the
Page Description Register (PDR).  There were two sets of Active Page
Registers (APRs), one for Kernel mode, and one for User mode.  There were 2
new instructions added: MFPI (Move from previous instruction space) and
MTPI (move to previous instruction space) as determined by the current
and previous modes of the PSW.

You could protect a page as read only, or read/write, or no access.

Floating point (single precision only) used a register as a pointer
to specify a stack address:

  (R)    High B argument address
  (R)+2  Low  B argument address
  (R)+4  High A argument address
  (R)+8  Low  A argument address

Result was in (R)+4: address of high part of answer, (R)+6: address of
low part of answer.


The pdp-11/45 was the second pdp-11 family member, following the pdp-11/20,
introduced in 1972.  It is the machine that much of early "modern" unix
was developed on.  (That's 30 years ago if you're counting...)

Memory management was built into the pdp-11/45.  There were separate
Instruction (I) and Data (D) spaces in each of the modes: Kernel,
Supervisor, and User.  Each mode had 8 I pages and 8 pages of D space.
Pages could be 32 to 4096 words.  Protection and relocation were provided
on a per-page basis.  There were three bits in the PDR for access control:

000 non-resident abort all accesses
001 read-only    abort on write attempt; memory management trap on read
010 read-only    abort on write attempt
011 unused       abort all accesses (for future use)
100 read/write   memory management trap upon completion of a read or write
101 read/write   memory management trap upon completion of a write
110 read/write   no system trap/abort action
111 unused       abort all accesses (for future use)


Two new opcodes were added, MFPD Move from previous data space, and MTPD
Move to previous data space; MFPI and MTPI were there, also.

The 11/45 floating point processor was optional.  It handled single- and
double-precision, and had six 64-bit floating point accumulators, and was
an independent co-processor with overlapped execution.  It could also be
set into "integer" mode or "long integer mode".  It was a kick-ass floating
point processor.


(Sorry for the diversion down memory lane...)

-Mike