On Sat, 17 Jul 1999 itojun@iijlab.net wrote:

> >If you do get an SMP kernel built, perhaps you could make it available
> >somewhere?  A friend has an SMP box, and we have a number at work,
> >it would be cool to boot a test kernel and at least see the second
> >CPU spin up. :)
> 
> 	Is it considered a bad thing to commit the above, with necessary
> 	care to keep non-SMP build as before? (make sure to #ifdef)

I should think not. After all, when I boot my Sparc these days I see:

NetBSD 1.4G (7THSUN) #4: Sun Jul 18 07:40:53 EDT 1999
    cjs@7thsun.cynic.net:/export/co/current/src/sys/arch/sparc/compile/7THSUN
...
cpu0 at mainbus0: mid 8: TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU
cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external (32 b/l): cache enabled
cpu1 at mainbus0: mid 10: TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU
cpu1: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external (32 b/l): cache enabled
...

Christos said yesterday that he thinks it's maybe a thousand or so
lines of code to get `big lock' SMP working. Perhaps he'll cons up
something we can play with.

cjs
-- 
Curt Sampson  <cjs@cynic.net>   917 532 4208   De gustibus, aut bene aut nihil.
The most widely ported operating system in the world: http://www.netbsd.org