Subject: Re: SMP API things, lock debugging, etc.
To: Jason Thorpe <thorpej@nas.nasa.gov>
From: Neil A. Carson <neil@causality.com>
List: tech-smp
Date: 07/27/1999 10:05:47
'iya,

Jason Thorpe wrote:

> IMPORTANT NOTE
> --------------
> 
> Some people have suggested that a data type `cpuid_t' be introduced to
> hold CPU identifiers.  After some consideration, I have concluded that
> the type `unsigned long' is preferable for the following reasons:

You could always typedef cpuid_t ulong, no? But the stuff just needs to
work first, anyway :)

> DATA STRUCTURES
> ---------------

>                 This structure will export the following members if
>                 the DIAGNOSTIC or LOCKDEBUG CPP symbols are defined:
> 
>                 - u_long ci_spin_locks: number of spin locks held by
>                   this processor
> 
>                 - u_long ci_simple_locks: number of simple locks held
>                   by this processor

In this sense, what's the difference between a simple lock and a spin
lock? Your simple locks seem to spin... Or by 'spin lock' do you mean
one that's used in IRQ context as well?

>                 This is an array of cpu_info structures declared and allocated
>                 in a machine-dependent source file.  It must be allocated
>                 and initialized before any machine-independent code is
>                 executed during the bootstrap process.  This array will
>                 be indexed by the value returned by the `cpu_number()'
>                 function.
> 
>                 cpu_info[] will be referenced in <sys/proc.h> by the
>                 following code block:
> 
> #if defined(MULTIPROCESSOR)
> #define curproc         cpu_info[cpu_number()].ci_curproc
> #else
> extern struct proc      *curproc;
> #endif

Why not just put the stuff in a separate physical page on each
processor, and map it to the same virtual address? OK, so you will need
to access each CPUs array from another, so simply map all NCPU pages in
a location they all know about, and then doubly map 'my CPU page' at the
same address in each CPU. Does that make sense?

Other than that, looks fine. What about IPI considerations for stuff
like TLB shootdown on multiple processors, etc? Or will that be part of
the per-platform pmap rather than the 'multiprocessor HAL?' I guess so.

How about calls to start and stop a processor, and freeze another CPU?

Just the usual senseless jaber from me :) Good stuff.

	Cheers,

	Neil