On Wed, Jun 12, 2002 at 03:54:29PM +0930, Brett Lymn wrote:
> On Wed, Jun 12, 2002 at 01:01:18AM +0000, Ken Seefried wrote:
> > 
> > Sparc32 supports all sorts of odd combos of asymetrical clock speeds.  My 
> > own SS20 has been running 2x100MHz + 1x90MHz ROSS CPUs under Linux and 
> > Solaris for quite some time.  It actually came to me as a 2x100MHz ROSS + 
> > 1x75MHz Hypersparc that had been running Solaris for a while. 
> > 
> 
> Interesting... our SS10 definitely wedge solid, the processors by
> themselves were ok.  As I said, I knew the mbus was supposed to allow
> it but the official word from sun was "not tested".

You almost certainly need two (sparc) processors from the same family.
Various parts of the mmu/cache/register window differ between them,
some of them don't do bus snooping - so wont run in an SMP environment.
(unfortunately I can't remember which ones were which...)

	David

-- 
David Laight: david@l8s.co.uk