Re: make: conditionals inside muti-line commands

[christos%astron.com@localhost (Christos Zoulas)]

In article <20150713183102.GJ576%trav.math.uni-bonn.de@localhost>,
Edgar Fuß  <ef%math.uni-bonn.de@localhost> wrote:
>I would like to simplify Makefile fragments like
>
>foobar:
>	cp /dev/null ${.TARGET}
>.ifdef(foo)
>	printf "foo=%s\n" "${foo}" >>${.TARGET}
>.endif
>.ifdef(bar)
>	printf "bar=%s\n" "${bar}" >>${.TARGET}
>.endif
>
>into something like
>
>foobar:
>	{\
>.ifdef(foo)
>		printf "foo=%s\n" "${foo}";\
>.endif
>.ifdef(bar)
>		printf "bar=%s\n" "${bar}";\
>.endif
>	} >${.TARGET}
>
>but I get error messages about open conditionals.
>
>Is this a bug?
>
>Is there another way to achieve what I want without opening the target 
>multiple times?
>


foobar:
	( \
	${foo:Dfalse:Utrue} || echo foo=${foo}; \
	${bar:Dfalse:Utrue} || echo bar=${bar}; \
	) > ${.TARGET}

christos