Re: make: dealing with targets with multiple outputs

[David Laight <david%l8s.co.uk@localhost>]

On Fri, Jun 07, 2019 at 05:43:24PM +0000, David Holland wrote:
> On Fri, May 31, 2019 at 11:06:22AM -0700, Simon J. Gerraty wrote:
>  > > We already have a solution for this problem, it's just waiting for
>  > > someone to find time to implement it.
>  > > 
>  > > Namely: given multiple targets on the left, don't schedule them in
>  > > parallel, and after building the first one check to see how many of
>  > > the others also got knocked off at the same time.
>  > 
>  > Couple that with a special target to trigger it - sounds good.
>  > That way you avoid the need to rewrite lots of makefiles with .for loops
> 
> No, the special target should be for the unusual case.
> 
> The usual case is:
> 
>    y.tab.c y.tab.h: foo.y
>            $(YACC) -d foo.y
> 
> The unusual case is:
> 
>    foo.o bar.o baz.o: $(@:.o=.c)
>            $(CC) $(@:.o=.c)
> 
> It's the unusual case that expects to run the recipe more than once.
> Few real makefiles are written in this form because it doesn't work
> very well to derive source names from target names. (And it doesn't
> work and hasn't ever worked at all except in BSD make, as best as I
> know.)

(I'm not dead!)

$(OBJS): $(HEADERS)
Is common - but doesn't have any rules.
(They usually come from the .c.o suffix rule.)

ISTR that:
$(OBJS): $$(@:.o=.c)
is valid in SYSV make (from 30+ years ago).
(But that might be after I fixed 'suffix translations on dynamic dependencies'.)

GNU make has its pattern match syntax - and that does get used.

I suspect there are far more cases of your 'unusual case' than you expect.
There are plenty of makefiles that generate a list of object files and
then rely on make to find the sources.
If your object tree matches the source tree then you get:
$(CC_OBJS): $(SRC_DIR)/$(@:.o=.c)
	$(CC) -o $@ $*

	David