tech-toolchain archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: Tiny allocations alignment requirements vs. jemalloc



On Thu, Feb 06, 2025 at 10:59:12AM +0100, Martin Husemann wrote:
> And I would also suggest to remove the (now ineffective) gcc change, or
> replace it with something better - ideally including jemalloc headers
> directly to get LG_QUANTUM, then assert that against MALLOC_ABI_ALIGNMENT
> and rely on the jemalloc build to verify SC_LG_TINY_MIN vs. LG_QUANTUM.

I looked at it the other way around: MALLOC_ABI_ALIGNMENT is quite trivial
defined and I ended up with the patch below.

I think it is needed and correct, but I might be overlooking something.

Unfortunately it does neither fix the arm nor the mipsn64 fallout I see
from the jemalloc switch.

Side note: our aarch64 gcc configuration is an outsider because it only
expects 8 byte alignment, while all other aarch64 expect 16 byte. We
could fix that too while fidling with jemalloc here.

Martin



Index: gpl3/gcc/dist/gcc/tree-ssa-ccp.cc
===================================================================
RCS file: /cvsroot/src/external/gpl3/gcc/dist/gcc/tree-ssa-ccp.cc,v
retrieving revision 1.4
diff -u -p -r1.4 tree-ssa-ccp.cc
--- gpl3/gcc/dist/gcc/tree-ssa-ccp.cc	1 Jul 2024 05:31:10 -0000	1.4
+++ gpl3/gcc/dist/gcc/tree-ssa-ccp.cc	7 Feb 2025 11:41:44 -0000
@@ -4643,45 +4643,3 @@ make_pass_post_ipa_warn (gcc::context *c
 {
   return new pass_post_ipa_warn (ctxt);
 }
-
-#if defined(__NetBSD__) && defined(NETBSD_NATIVE)
-/*
- * This is a big, ugly, temporary hack:
- *    http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59958
- * To make sure we have configured all our targets correctly, mimic the
- * #ifdef cascade from src/lib/libc/stdlib/jemalloc.c here and compile
- * time assert that the value matches gcc's MALLOC_ABI_ALIGNMENT here.
- */
-
-#if defined(__hppa__)
-#define	JEMALLOC_TINY_MIN_2POW	4
-#elif defined(__alpha__) || defined(__amd64__) || defined(__sparc64__)	\
-     ||	(defined(__arm__) && defined(__ARM_EABI__)) \
-     || defined(__ia64__) || defined(__powerpc__) \
-     || defined(__aarch64__) \
-     || ((defined(__mips__) || defined(__riscv__)) && defined(_LP64))
-#define	JEMALLOC_TINY_MIN_2POW	3
-#endif
-
-#ifndef JEMALLOC_TINY_MIN_2POW
-#define	JEMALLOC_TINY_MIN_2POW	2
-#endif
-
-/* make sure we test the (native) 64bit variant for targets supporting -m32 */
-#undef	TARGET_64BIT
-#ifdef _LP64
-#define	TARGET_64BIT	1
-#else
-#define	TARGET_64BIT	0
-#endif
-
-/* ARM has a non-constant MALLOC_ABI_ALIGNMENT since GCC 5.  */
-#if !defined(__arm__)
-#ifdef __CTASSERT
-__CTASSERT((8<<JEMALLOC_TINY_MIN_2POW) == MALLOC_ABI_ALIGNMENT);
-#else
-#error compiling on an older NetBSD version?
-#endif
-#endif
-
-#endif
Index: bsd/jemalloc/include/jemalloc/internal/size_classes.h
===================================================================
RCS file: /cvsroot/src/external/bsd/jemalloc/include/jemalloc/internal/size_classes.h,v
retrieving revision 1.4
diff -u -p -r1.4 size_classes.h
--- bsd/jemalloc/include/jemalloc/internal/size_classes.h	28 Mar 2019 11:56:56 -0000	1.4
+++ bsd/jemalloc/include/jemalloc/internal/size_classes.h	7 Feb 2025 11:43:14 -0000
@@ -35,7 +35,16 @@
  */
 
 #define LG_SIZE_CLASS_GROUP	2
+
+#ifdef __NetBSD__
+#if defined(_LP64) || defined(__arm__)
+#define LG_TINY_MIN		4
+#else
+#define LG_TINY_MIN		3
+#endif
+#else
 #define LG_TINY_MIN		3
+#endif
 
 #if (LG_SIZEOF_PTR == 2 && LG_TINY_MIN == 3 && LG_QUANTUM == 3 && LG_PAGE == 12)
 #define SIZE_CLASSES \



Home | Main Index | Thread Index | Old Index