Re: SmartFirmware interrupts

[Matt Sealey <matt%genesi-usa.com@localhost>]

Tim Rightnour wrote:
> On 18-Oct-2007 Frank Wille wrote:
> > Usually the first 8259 PIC is at I/O address 0x20 and the second at 0xa0. But
> > the I/O space of the first pci-node is e.g. mapped at 0xfe000000 on the Peg2.
>
> I haven't gotten this far in the IO stuff on the Pegasos yet, but the IO stuff
> on ppc is generally different than you would find on a real PC.
>
> Prep is a simpler example of this.  You have isa @ 0x80000000.  So, if you want
> to talk to a com port, its 0x800002f8.
>
> Basically, for things on the isa bus, you use an offset of where the IO space
> is.

This is TMI and you all know this, but..

The basic difference is that a PCI-based x86 system has 3 (THREE!!!!!) seperate
magical address spaces - IO space, memory mapped space, and PCI config space.
Some might say two, but.. well.. Intel describe it this way.

If you write to 0x2f8 using 'outb' you are not writing a byte to memory location
0x3f8. You are writing a byte to "magical io port" 0x2f8. Writing to memory
location 0x3f8 (with 'mov' or so) does not generally affect the io port.

PowerPC (and any other modern CPU) does not have these. It has one address
space, so, 0x2f8 really really is the memory location 0x2f8, under all
circumstances. The problem here is that 0x2f8 is the zero page.. and most
people like to use that to trap null pointer access and wraparounds from
trashing memory. Oh well.

So, what you have to do, is map "IO" into memory (actually an x86 PC does
this too, but the host controller snoops low-memory port accesses and
redirects them here) at some ridiculously high address. We can do that on
Pegasos but it would break a ton of stuff (actually.. the firmware does do
this for the x86 emulation on Pegasos, it makes the AGP port easier to
use).

> What this all boils down to, is that because they don't tell us what is really
> going on in this machine, we have to hardcode a bunch of stuff to say if we are
> on a pegasos do this or that.  Apparently it has an 8259, so we just apply the
> isa offset to the standard 8259 io offset and ping it.

No. Just use the i8259. It really is an i8259 - the same i8259 you have in any
PC southbridge that would be mapped on a PC to io port 0x2fb. It is not a
real i8259 Intel chip, but it is a darn clever mimick of one. The same goes for
the "COM port", the "ISA controller" and the "PS/2" port. These are, in fact,
PCI devices. On a PC they capture IO addressing of the low ports. On PowerPC,
there are no IO addressing or IO ports of any kind :D

You can very easily assume there are two controllers, as this has been the
case since what.. 1987? 20 years later we are still debating how a totally
fake chipset on a totally braindead architecture handles things.. just take
the assumption :D

> Of course, they did something rather odd with the isa too, they appear to just
> emulate an isa bus, which I don't really understand, and there is no isa IO/MEM
> map on the Pegasos II.  Apparently it's all just PCI space, so thats what I'm
> trying to deal with now (in a way that won't break other machines).  Shouldn't
> be too hard though, it will just take me some time to work it all out.

We do not emulate an ISA bus. Genesi, bplan and the Gods In Heaven did not do
anything weird with the Pegasos - this is standard behaviour for a PC99
southbridge. What you have is actually technically an LPC bus - it acts a lot
like an ISA bus for compatibility with the PC BIOS. It is in fact a PCI
device that responds to PCI IO space, just without the weird PC-BIOS IO
snooping, without the stupid edge/level trigger distinction.

Just treat the offset like the magical pointer into IO space and it is no
different whatsoever - no different as in outb(0x0 + 0x2fb, 0xff) is no 
different
to outb(0xf1000000 + 0x2fb, 0xff) on PowerPC. From software it *IS* an i8259
interrupt controller, as it is on a PC, and from software there *IS* an ISA
bus as it is on a PC, but neither have really, actually existed since the
Pentium came out (what was that, 1993?). There's a legacy ISA/XT DMA controller
in there (which can only address 16MB of memory!) and an 8042 keyboard
controller (it bloody well isn't!) and so on and so forth, while they do not
really exist, you may as well assume they do because the VIA datasheet says
if you poke this register, it will very much act this way.

If you want the Via datasheet you can google for it ("VT8231 Datasheet")
and get all the skinny on the crazy x86 weirdness in there.

--
Matt Sealey <matt%genesi-usa.com@localhost>
Genesi, Manager, Developer Relations