Re: SmartFirmware interrupts

[Matt Sealey <matt%genesi-usa.com@localhost>]

Frank Wille wrote:
> Matt Sealey wrote:
>
> > > Hm. Which information does SmartFirmware provide about it? The only thing
> > > I found was "8259-IRQ at f1000cb4". This is for the ISA interrupts?
> > It's connected in a cascade to the Marvell chip. You do not need to know
> > how the Marvell PIC works. Just use the 8259 (as is present in every PC
> > known to man..)
>
> Addendum: After looking at the source, I'm still confused.
>
> Usually the first 8259 PIC is at I/O address 0x20 and the second at 0xa0. But
> the I/O space of the first pci-node is e.g. mapped at 0xfe000000 on the Peg2.
>
> How does an address of 0xf1000cb4 help me now? Is it the memory-mapped
> base address of the first PIC? But where are the registers for the second
> one? 0x80 bytes from there?

Usually. One thing you can assume is that everything on the PCI bus is mapped
to IRQ 9 anyway - because, it really is. Everything else, you can assume a
standard PCI interrupt number (14/15 for IDE) as these are handled by the ISA
bridge and trapped and transparently routed to IRQ 9.

I am fairly sure Pegasos includes the interrupt numbers (do you have the
latest firmware 1.2?) because Linux patches them. The IDE controller has
0x14 and 0x15 instead of decimal 14 and 15, for example.. it is not a
proper, full interrupt-map but it certain is more than enough to get the
system up (especially considering you have an i8259 interrupt controller
and there is no fancy routing that is not hidden via some PC-style southbridge
technology.

--
Matt Sealey <matt%genesi-usa.com@localhost>
Genesi, Manager, Developer Relations