Re: CVS commit: src/sys/dev/ic

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

dyoung%pobox.com@localhost wrote:

> Ok.  I was pretty sure that ath, atw, rtw, sip, and tlp properly
> synchronized descriptors.  I hope that people will file PRs against those
> drivers that do not.  I intended to get the synchronization absolutely
> correct with atw and rtw, but I may still have botched it.

Well, I know they are implemented to do so, but I'm not sure if
they are tested on real non DMA-cache coherent machines without
BUS_DMA_COHERENT.

For example, tulip.c has the following code in tlp_rxintr():
---
                TULIP_CDRXSYNC(sc, i,
                    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
                rxstat = le32toh(sc->sc_rxdescs[i].td_status);
                if (rxstat & TDSTAT_OWN) {
                        /*
                         * We have processed all of the receive buffers.
                         */
                        break;
                }
---
But we should also have a BUS_DMASYNC_PREREAD call after poking td_status
otherwise CPU will refer lingering cached data and won't notice
updated data in the descriptor. AFAIK, there are few drivers which
have such PREREAD calls after checking "OWN"ed bit in descriptors.

Furthermore, on some archtectures PREREAD sync call is implemented
as "invalidate with writeback" (by hardware limitation, or just to
handle non-cacheline-aligned sync). In such case, there is no way to
avoid race condition if the descriptor is updated by the busmaster
between CPU poke and BUS_DMASYNC_PREREAD call.

So, I'm afraid BUS_DMA_COHERENT is almost mandatory for now
unless the target device is designed for such non coherent systems.
---
Izumi Tsutsui