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CVS commit: src/sys/arch/evbmips/ingenic
Module Name: src
Committed By: skrll
Date: Fri May 19 07:40:58 UTC 2017
Modified Files:
src/sys/arch/evbmips/ingenic: autoconf.c clock.c cpu.c machdep.c
mainbus.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbmips/ingenic/autoconf.c \
src/sys/arch/evbmips/ingenic/cpu.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbmips/ingenic/clock.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/evbmips/ingenic/machdep.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbmips/ingenic/mainbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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