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CVS commit: src/sys/arch/mips/ingenic
Module Name: src
Committed By: skrll
Date: Fri May 19 07:43:31 UTC 2017
Modified Files:
src/sys/arch/mips/ingenic: apbus.c ingenic_com.c ingenic_dme.c
jzfb_regs.h jziic.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/ingenic/apbus.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/ingenic/ingenic_com.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/ingenic/ingenic_dme.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/jzfb_regs.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/ingenic/jziic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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