Re: USB troubles with SB600/SB700 chipsets

[David Young <dyoung%pobox.com@localhost>]

On Sun, May 17, 2009 at 11:40:22PM +0200, Christoph Egger wrote:
> Index: sys/dev/pci/ehci_pci.c
> ===================================================================
> RCS file: /cvsroot/src/sys/dev/pci/ehci_pci.c,v
> retrieving revision 1.44
> diff -u -p -r1.44 ehci_pci.c
> --- sys/dev/pci/ehci_pci.c    26 Apr 2009 09:47:31 -0000      1.44
> +++ sys/dev/pci/ehci_pci.c    17 May 2009 21:36:48 -0000
> @@ -74,9 +74,87 @@ struct ehci_pci_softc {
>       void                    *sc_ih;         /* interrupt vectoring */
>  };
>  
> +static int (*ehci_pci_applyquirks)(struct ehci_pci_softc *) = NULL;

If ehci_pci_applyquirks is set, and a non-AMD ehci(4) instance is
subsequently initialized, ehci_pci_attach will apply the wrong quirk,
won't it?  Please, add a softc member for this.

> +static int
> +amdehci_applyquirks(struct ehci_pci_softc *sc)
> +{
> +        uint8_t value;
> +
> +        aprint_normal_dev(sc->sc.sc_dev,
> +            "applying AMD SB600/SB700 USB freeze workaround\n");
> +        value = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x53);
> +        pci_conf_write(sc->sc_pc, sc->sc_tag, 0x53, value | (1U << 3));
> +
> +        return 0;
> +}

amdehci_applyquirks() probably does not do what you think.
pci_conf_{read,write}(9) read/write 32-bit configuration registers
aligned at 32-bit boundaries.  A DIAGNOSTIC kernel will panic.
Otherwise, the system may trap to the debugger beacuse of the unaligned
access.

Please name both the register (0x50?) and the bit that you set (bit
27?), and use those names.  Use __BIT() to be clear.

BTW, is 0x50/0x53 referenced by the PCI Capability List?  Does your
rudimentary knowledge of the register come from other code or from
official documentation?

Dave

-- 
David Young             OJC Technologies
dyoung%ojctech.com@localhost      Urbana, IL * (217) 278-3933