Re: [guruplug] mvgbe1 no PHY found

[Dave Mills <dmills%63bit.com@localhost>]

>No, the PHYs can be accessed through the SMI register for each port.

>The problem is that the wrong bus space handle is being used in the
>mvgbe_miibus_* functions, they should use the one for the port not
>the controller, the offset for the SMI register needs changing too.

PHY Address Register Port0: 0x72004, Port1: 0x76004
(P554 88F6180, 88F6190,88F6192, and 88F6281 Integrated Controller Functional
Specifications)

I checked the addresses read by the mvgbe_miibus_* functions (bus space
handle + MVGBE_SMI) and they match up to the offsets quoted above
(+0xf1000000 for register base address)
SMI register is a controller register not a port register.
(if we were using the port bus space handle we would be reading offsets of
0x72400+ and 0x76400+)

>There is only one controller in the CPU used in the Sheevaplug and
>Guruplug, it has two ports.

"The 88F6192 and 88F6281 implement two GbE controllers"
(P113 88F6180, 88F6190,88F6192, and 88F6281 Integrated Controller Functional
Specifications)

Dave Mils
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