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Re: New CPUID_TO_{FAMILY,MODEL} macros.
(2013/11/13 7:33), Christos Zoulas wrote:
> In article <52827D83.7020803%execsw.org@localhost>,
> SAITOH Masanobu <msaitoh%execsw.org@localhost> wrote:
>> Today, I fixed three or more bugs which related to the calculation of the CPU
>> family and model. I'd like to change the CPU family/model related macros.
>>
> [stuff deleted]
>
> This all LGTM!
>
> christos
Thanks.
The last patch had a bug in CPUID_TO_MODEL() macro.
Updated patch:
Index: sys/arch/x86/include/specialreg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/include/specialreg.h,v
retrieving revision 1.71
diff -u -r1.71 specialreg.h
--- sys/arch/x86/include/specialreg.h 21 Oct 2013 06:11:49 -0000 1.71
+++ sys/arch/x86/include/specialreg.h 13 Nov 2013 04:57:25 -0000
@@ -192,19 +192,30 @@
"\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \
"\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ"
-#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)
-#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)
-#define CPUID2STEPPING(cpuid) ((cpuid) & 0xf)
+/* CPUID Fn00000001 %eax */
+
+#define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf)
+#define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf)
+#define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf)
/*
- * The Extended family bits should only be inspected when CPUID2FAMILY()
+ * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY()
* returns 15. They are use to encode family value 16 to 270 (add 15).
- * The Extended model hits are the high 4 bits of the model.
+ * The Extended model bits are the high 4 bits of the model.
* They are only valid for family >= 15 or family 6 (intel, but all amd
* family 6 are documented to return zero bits for them).
*/
-#define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
-#define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
+#define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
+#define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
+
+/* The macros for the Display Family and the Display Model */
+#define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \
+ + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \
+ ? 0 : CPUID_TO_EXTFAMILY(cpuid)))
+#define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \
+ | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \
+ && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \
+ ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
/*
* Intel Deterministic Cache Parameter Leaf
Index: usr.sbin/cpuctl/arch/i386.c
===================================================================
RCS file: /cvsroot/src/usr.sbin/cpuctl/arch/i386.c,v
retrieving revision 1.49
diff -u -r1.49 i386.c
--- usr.sbin/cpuctl/arch/i386.c 7 Nov 2013 18:59:01 -0000 1.49
+++ usr.sbin/cpuctl/arch/i386.c 13 Nov 2013 04:57:26 -0000
@@ -897,7 +897,7 @@
static void
via_cpu_probe(struct cpu_info *ci)
{
- u_int stepping = CPUID2STEPPING(ci->ci_signature);
+ u_int stepping = CPUID_TO_STEPPING(ci->ci_signature);
u_int descs[4];
u_int lfunc;
@@ -1175,7 +1175,7 @@
u_int descs[4];
u_int lfunc;
- stepping = CPUID2STEPPING(ci->ci_signature);
+ stepping = CPUID_TO_STEPPING(ci->ci_signature);
/*
* Determine the largest extended function value.
@@ -1349,12 +1349,8 @@
ci->ci_signature = descs[0];
/* Extract full family/model values */
- ci->ci_family = CPUID2FAMILY(ci->ci_signature);
- ci->ci_model = CPUID2MODEL(ci->ci_signature);
- if (ci->ci_family == 15)
- ci->ci_family += CPUID2EXTFAMILY(ci->ci_signature);
- if (ci->ci_family == 6 || ci->ci_family == 15)
- ci->ci_model += CPUID2EXTMODEL(ci->ci_signature) << 4;
+ ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature);
+ ci->ci_model = CPUID_TO_MODEL(ci->ci_signature);
/* Brand is low order 8 bits of ebx */
ci->ci_brand_id = descs[1] & 0xff;
@@ -1676,7 +1672,8 @@
else
brand = amd_brand_name;
}
- if (CPUID2FAMILY(ci->ci_signature) == 0xf) {
+ if (CPUID_TO_BASEFAMILY(ci->ci_signature)
+ == 0xf) {
/* Identify AMD64 CPU names. */
const char *tmp;
tmp = amd_amd64_name(ci);
@@ -1720,7 +1717,7 @@
(((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100);
aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x",
- ci->ci_family, ci->ci_model, CPUID2STEPPING(ci->ci_signature));
+ ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature));
if (ci->ci_signature != 0)
aprint_normal(" (id %#x)", ci->ci_signature);
aprint_normal("\n");
Index: sys/arch/x86/acpi/acpi_cpu_md.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/acpi/acpi_cpu_md.c,v
retrieving revision 1.72
diff -u -r1.72 acpi_cpu_md.c
--- sys/arch/x86/acpi/acpi_cpu_md.c 6 Dec 2012 04:43:29 -0000 1.72
+++ sys/arch/x86/acpi/acpi_cpu_md.c 13 Nov 2013 04:57:26 -0000
@@ -243,10 +243,7 @@
x86_cpuid(0x80000007, regs);
- family = CPUID2FAMILY(ci->ci_signature);
-
- if (family == 0xf)
- family += CPUID2EXTFAMILY(ci->ci_signature);
+ family = CPUID_TO_FAMILY(ci->ci_signature);
switch (family) {
@@ -547,10 +544,7 @@
if ((sc->sc_flags & ACPICPU_FLAG_P_FIDVID) != 0)
msr.ps_flags |= ACPICPU_FLAG_P_FIDVID;
- family = CPUID2FAMILY(ci->ci_signature);
-
- if (family == 0xf)
- family += CPUID2EXTFAMILY(ci->ci_signature);
+ family = CPUID_TO_FAMILY(ci->ci_signature);
switch (family) {
Index: sys/arch/x86/pci/amdtemp.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/pci/amdtemp.c,v
retrieving revision 1.17
diff -u -r1.17 amdtemp.c
--- sys/arch/x86/pci/amdtemp.c 12 Nov 2013 15:08:01 -0000 1.17
+++ sys/arch/x86/pci/amdtemp.c 13 Nov 2013 04:57:26 -0000
@@ -199,16 +199,14 @@
if (cpu_signature == 0x0)
return 0;
- family = CPUID2FAMILY(cpu_signature);
- if (family == 0xf)
- family += CPUID2EXTFAMILY(cpu_signature);
+ family = CPUID_TO_FAMILY(cpu_signature);
/* Errata #319: This has been fixed in Revision C2. */
if (family == 0x10) {
- if (CPUID2MODEL(cpu_signature) < 4)
+ if (CPUID_TO_BASEMODEL(cpu_signature) < 4)
return 0;
- if (CPUID2MODEL(cpu_signature) == 4
- && CPUID2STEPPING(cpu_signature) < 2)
+ if (CPUID_TO_BASEMODEL(cpu_signature) == 4
+ && CPUID_TO_STEPPING(cpu_signature) < 2)
return 0;
}
@@ -238,9 +236,7 @@
/* If we hit this, then match routine is wrong. */
KASSERT(cpu_signature != 0x0);
- sc->sc_family = CPUID2FAMILY(cpu_signature);
- if (sc->sc_family == 0xf)
- sc->sc_family += CPUID2EXTFAMILY(cpu_signature);
+ sc->sc_family = CPUID_TO_FAMILY(cpu_signature);
KASSERT(sc->sc_family >= 0xf);
@@ -379,7 +375,7 @@
sc->sc_rev = amdtemp_core[i].rev[3];
aprint_normal(": core rev %.4s%.1x",
amdtemp_core[i].rev,
- CPUID2STEPPING(cpu_signature));
+ CPUID_TO_STEPPING(cpu_signature));
switch (amdtemp_core[i].cpu[j].socket) {
case K8_SOCKET_AM2:
Index: sys/arch/x86/x86/coretemp.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/coretemp.c,v
retrieving revision 1.30
diff -u -r1.30 coretemp.c
--- sys/arch/x86/x86/coretemp.c 12 Nov 2013 15:58:38 -0000 1.30
+++ sys/arch/x86/x86/coretemp.c 13 Nov 2013 04:57:27 -0000
@@ -217,8 +217,8 @@
uint32_t model, stepping;
uint64_t msr;
- model = CPUID2MODEL(ci->ci_signature);
- stepping = CPUID2STEPPING(ci->ci_signature);
+ model = CPUID_TO_MODEL(ci->ci_signature);
+ stepping = CPUID_TO_STEPPING(ci->ci_signature);
/*
* Check if the MSR contains thermal
@@ -259,11 +259,9 @@
uint32_t family, model, stepping;
uint64_t msr;
- family = CPUID2FAMILY(ci->ci_signature);
- model = CPUID2MODEL(ci->ci_signature);
- if ((family == 0xf) || (family == 0x6))
- model |= CPUID2EXTMODEL(ci->ci_signature) << 4;
- stepping = CPUID2STEPPING(ci->ci_signature);
+ family = CPUID_TO_FAMILY(ci->ci_signature);
+ model = CPUID_TO_MODEL(ci->ci_signature);
+ stepping = CPUID_TO_STEPPING(ci->ci_signature);
sc->sc_tjmax = 100;
Index: sys/arch/x86/x86/cpu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/cpu.c,v
retrieving revision 1.105
diff -u -r1.105 cpu.c
--- sys/arch/x86/x86/cpu.c 12 Nov 2013 16:15:54 -0000 1.105
+++ sys/arch/x86/x86/cpu.c 13 Nov 2013 04:57:27 -0000
@@ -592,10 +592,10 @@
/*
* Must be a K6-2 Step >= 7 or a K6-III.
*/
- if (CPUID2FAMILY(ci->ci_signature) == 5) {
- if (CPUID2MODEL(ci->ci_signature) > 8 ||
- (CPUID2MODEL(ci->ci_signature) == 8 &&
- CPUID2STEPPING(ci->ci_signature) >= 7)) {
+ if (CPUID_TO_FAMILY(ci->ci_signature) == 5) {
+ if (CPUID_TO_MODEL(ci->ci_signature) > 8 ||
+ (CPUID_TO_MODEL(ci->ci_signature) == 8 &&
+ CPUID_TO_STEPPING(ci->ci_signature) >= 7)) {
mtrr_funcs = &k6_mtrr_funcs;
k6_mtrr_init_first();
mtrr_init_cpu(ci);
Index: sys/arch/x86/x86/cpu_topology.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/cpu_topology.c,v
retrieving revision 1.7
diff -u -r1.7 cpu_topology.c
--- sys/arch/x86/x86/cpu_topology.c 12 Nov 2013 16:35:57 -0000 1.7
+++ sys/arch/x86/x86/cpu_topology.c 13 Nov 2013 04:57:27 -0000
@@ -57,9 +57,7 @@
uint32_t descs[4], lextmode;
apic_id = ci->ci_initapicid;
- cpu_family = CPUID2FAMILY(ci->ci_signature);
- if (cpu_family == 0xf)
- cpu_family += CPUID2EXTFAMILY(ci->ci_signature);
+ cpu_family = CPUID_TO_FAMILY(ci->ci_signature);
/* Initial values. */
ci->ci_package_id = apic_id;
Index: sys/arch/x86/x86/cpu_ucode_amd.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/cpu_ucode_amd.c,v
retrieving revision 1.6
diff -u -r1.6 cpu_ucode_amd.c
--- sys/arch/x86/x86/cpu_ucode_amd.c 6 Jul 2013 12:03:11 -0000 1.6
+++ sys/arch/x86/x86/cpu_ucode_amd.c 13 Nov 2013 04:57:27 -0000
@@ -95,9 +95,7 @@
uint32_t family;
struct cpu_info *ci = curcpu();
- family = CPUID2FAMILY(ci->ci_signature);
- if (family == 0xf)
- family += CPUID2EXTFAMILY(ci->ci_signature);
+ family = CPUID_TO_FAMILY(ci->ci_signature);
return family;
}
Index: sys/arch/x86/x86/cpu_ucode_intel.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/cpu_ucode_intel.c,v
retrieving revision 1.3
diff -u -r1.3 cpu_ucode_intel.c
--- sys/arch/x86/x86/cpu_ucode_intel.c 6 Jul 2013 12:11:54 -0000 1.3
+++ sys/arch/x86/x86/cpu_ucode_intel.c 13 Nov 2013 04:57:27 -0000
@@ -76,7 +76,7 @@
struct cpu_ucode_version_intel1 data;
if (ucode->loader_version != CPU_UCODE_LOADER_INTEL1 ||
- CPUID2FAMILY(ci->ci_signature) < 6)
+ CPUID_TO_FAMILY(ci->ci_signature) < 6)
return EOPNOTSUPP;
if (!ucode->data)
return 0;
@@ -98,7 +98,7 @@
return firmware_open(fw_path, fwname, fwh);
cpu_signature = curcpu()->ci_signature;
- if (CPUID2FAMILY(cpu_signature) < 6)
+ if (CPUID_TO_FAMILY(cpu_signature) < 6)
return EOPNOTSUPP;
intel_getcurrentucode(&ucodeversion, &platformid);
Index: sys/arch/x86/x86/est.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/est.c,v
retrieving revision 1.27
diff -u -r1.27 est.c
--- sys/arch/x86/x86/est.c 8 Nov 2013 19:05:52 -0000 1.27
+++ sys/arch/x86/x86/est.c 13 Nov 2013 04:57:27 -0000
@@ -1080,8 +1080,8 @@
uint32_t family, model;
int bus_clock = 0;
- model = CPUID2MODEL(ci->ci_signature);
- family = CPUID2FAMILY(ci->ci_signature);
+ family = CPUID_TO_BASEFAMILY(ci->ci_signature);
+ model = CPUID_TO_MODEL(ci->ci_signature);
switch (family) {
Index: sys/arch/x86/x86/identcpu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/identcpu.c,v
retrieving revision 1.37
diff -u -r1.37 identcpu.c
--- sys/arch/x86/x86/identcpu.c 12 Nov 2013 16:13:56 -0000 1.37
+++ sys/arch/x86/x86/identcpu.c 13 Nov 2013 04:57:27 -0000
@@ -107,8 +107,8 @@
u_int descs[4];
u_int lfunc;
- family = CPUID2FAMILY(ci->ci_signature);
- model = CPUID2MODEL(ci->ci_signature);
+ family = CPUID_TO_FAMILY(ci->ci_signature);
+ model = CPUID_TO_MODEL(ci->ci_signature);
/*
* K5 model 0 has none of this info.
@@ -117,15 +117,6 @@
return;
/*
- * Get extended values for K8 and up.
- */
- if (family == 0xf)
- family += CPUID2EXTFAMILY(ci->ci_signature);
-
- if ((family == 0xf) || (family == 0x6))
- model |= CPUID2EXTMODEL(ci->ci_signature) << 4;
-
- /*
* Determine the largest extended function value.
*/
x86_cpuid(0x80000000, descs);
@@ -249,10 +240,10 @@
int flag;
if (cpu_vendor != CPUVENDOR_AMD ||
- CPUID2FAMILY(ci->ci_signature) != 5)
+ CPUID_TO_FAMILY(ci->ci_signature) != 5)
return;
- if (CPUID2MODEL(ci->ci_signature) == 0) {
+ if (CPUID_TO_MODEL(ci->ci_signature) == 0) {
/*
* According to the AMD Processor Recognition App Note,
* the AMD-K5 Model 0 uses the wrong bit to indicate
@@ -274,7 +265,7 @@
uint32_t descs[4];
if (cpu_vendor != CPUVENDOR_AMD ||
- CPUID2FAMILY(ci->ci_signature) < 6)
+ CPUID_TO_FAMILY(ci->ci_signature) < 6)
return;
/* Determine the extended feature flags. */
@@ -370,8 +361,8 @@
{
if (cpu_vendor != CPUVENDOR_CYRIX ||
- CPUID2FAMILY(ci->ci_signature) < 4 ||
- CPUID2FAMILY(ci->ci_signature) > 6)
+ CPUID_TO_FAMILY(ci->ci_signature) < 4 ||
+ CPUID_TO_FAMILY(ci->ci_signature) > 6)
return;
cpu_probe_cyrix_cmn(ci);
@@ -384,10 +375,10 @@
if (cpu_vendor != CPUVENDOR_IDT)
return;
- switch (CPUID2FAMILY(ci->ci_signature)) {
+ switch (CPUID_TO_FAMILY(ci->ci_signature)) {
case 5:
/* WinChip C6 */
- if (CPUID2MODEL(ci->ci_signature) == 4)
+ if (CPUID_TO_MODEL(ci->ci_signature) == 4)
ci->ci_feat_val[0] &= ~CPUID_TSC;
break;
case 6:
@@ -416,12 +407,12 @@
struct x86_cache_info *cai;
if (cpu_vendor != CPUVENDOR_IDT ||
- CPUID2FAMILY(ci->ci_signature) < 6)
+ CPUID_TO_FAMILY(ci->ci_signature) < 6)
return;
- family = CPUID2FAMILY(ci->ci_signature);
- model = CPUID2MODEL(ci->ci_signature);
- stepping = CPUID2STEPPING(ci->ci_signature);
+ family = CPUID_TO_FAMILY(ci->ci_signature);
+ model = CPUID_TO_MODEL(ci->ci_signature);
+ stepping = CPUID_TO_STEPPING(ci->ci_signature);
/* Determine the largest extended function value. */
x86_cpuid(0x80000000, descs);
@@ -556,7 +547,7 @@
{
if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 ||
- CPUID2FAMILY(ci->ci_signature) != 5)
+ CPUID_TO_FAMILY(ci->ci_signature) != 5)
return;
cpu_probe_cyrix_cmn(ci);
@@ -668,7 +659,8 @@
ci->ci_feat_val[0] = descs[3];
/* Determine family + class. */
- cpu_class = CPUID2FAMILY(ci->ci_signature) + (CPUCLASS_386 - 3);
+ cpu_class = CPUID_TO_FAMILY(ci->ci_signature)
+ + (CPUCLASS_386 - 3);
if (cpu_class > CPUCLASS_686)
cpu_class = CPUCLASS_686;
Index: sys/arch/x86/x86/intel_busclock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/intel_busclock.c,v
retrieving revision 1.16
diff -u -r1.16 intel_busclock.c
--- sys/arch/x86/x86/intel_busclock.c 12 Nov 2013 16:57:30 -0000 1.16
+++ sys/arch/x86/x86/intel_busclock.c 13 Nov 2013 04:57:28 -0000
@@ -94,12 +94,8 @@
int bus, bus_clock = 0;
uint32_t family, model;
- family = CPUID2FAMILY(ci->ci_signature);
- model = CPUID2MODEL(ci->ci_signature);
-
- /* Note that this function is called only when family != 0xf */
- if (family == 6)
- model |= CPUID2EXTMODEL(ci->ci_signature) << 4;
+ family = CPUID_TO_FAMILY(ci->ci_signature);
+ model = CPUID_TO_MODEL(ci->ci_signature);
switch (model) {
case 0x9: /* Pentium M (130 nm, Banias) */
@@ -284,7 +280,7 @@
default:
aprint_debug("%s: unknown i686 model %d, can't get bus clock",
device_xname(ci->ci_dev),
- CPUID2MODEL(ci->ci_signature));
+ CPUID_TO_MODEL(ci->ci_signature));
print_msr:
/*
* Show the EBL_CR_POWERON MSR, so we'll at least have
@@ -304,7 +300,7 @@
int bus, bus_clock = 0;
msr = rdmsr(MSR_EBC_FREQUENCY_ID);
- if (CPUID2MODEL(ci->ci_signature) < 2) {
+ if (CPUID_TO_MODEL(ci->ci_signature) < 2) {
bus = (msr >> 21) & 0x7;
switch (bus) {
case 0:
@@ -317,14 +313,14 @@
aprint_debug("%s: unknown Pentium 4 (model %d) "
"EBC_FREQUENCY_ID value %d\n",
device_xname(ci->ci_dev),
- CPUID2MODEL(ci->ci_signature), bus);
+ CPUID_TO_MODEL(ci->ci_signature), bus);
break;
}
} else {
bus = (msr >> 16) & 0x7;
switch (bus) {
case 0:
- bus_clock = (CPUID2MODEL(ci->ci_signature) == 2) ?
+ bus_clock = (CPUID_TO_MODEL(ci->ci_signature) == 2) ?
10000 : 26666;
break;
case 1:
@@ -340,7 +336,7 @@
aprint_debug("%s: unknown Pentium 4 (model %d) "
"EBC_FREQUENCY_ID value %d\n",
device_xname(ci->ci_dev),
- CPUID2MODEL(ci->ci_signature), bus);
+ CPUID_TO_MODEL(ci->ci_signature), bus);
break;
}
}
Index: sys/arch/x86/x86/lapic.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/lapic.c,v
retrieving revision 1.46
diff -u -r1.46 lapic.c
--- sys/arch/x86/x86/lapic.c 12 Jun 2011 03:35:50 -0000 1.46
+++ sys/arch/x86/x86/lapic.c 13 Nov 2013 04:57:28 -0000
@@ -101,7 +101,7 @@
* to using it at this point. Be conservative and assume that the MSR
* is not present on the Pentium (is it?).
*/
- if (CPUID2FAMILY(curcpu()->ci_signature) >= 6) {
+ if (CPUID_TO_FAMILY(curcpu()->ci_signature) >= 6) {
lapic_base = (paddr_t)rdmsr(LAPIC_MSR);
if ((lapic_base & LAPIC_MSR_ADDR) == 0) {
lapic_base |= LAPIC_BASE;
Index: sys/arch/x86/x86/odcm.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/odcm.c,v
retrieving revision 1.2
diff -u -r1.2 odcm.c
--- sys/arch/x86/x86/odcm.c 2 Jun 2012 21:36:42 -0000 1.2
+++ sys/arch/x86/x86/odcm.c 13 Nov 2013 04:57:28 -0000
@@ -166,7 +166,7 @@
x86_cpuid(1, regs);
- switch (CPUID2STEPPING(regs[0])) {
+ switch (CPUID_TO_STEPPING(regs[0])) {
case 0x22: /* errata O50 P44 and Z21 */
case 0x24:
Index: sys/arch/x86/x86/patch.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/patch.c,v
retrieving revision 1.21
diff -u -r1.21 patch.c
--- sys/arch/x86/x86/patch.c 18 Apr 2010 23:47:51 -0000 1.21
+++ sys/arch/x86/x86/patch.c 13 Nov 2013 04:57:28 -0000
@@ -227,9 +227,9 @@
* sections. Apply workaround.
*/
if (cpu_vendor == CPUVENDOR_AMD &&
- (CPUID2FAMILY(cpu_info_primary.ci_signature) == 0xe ||
- (CPUID2FAMILY(cpu_info_primary.ci_signature) == 0xf &&
- CPUID2EXTMODEL(cpu_info_primary.ci_signature) < 0x4))) {
+ (CPUID_TO_FAMILY(cpu_info_primary.ci_signature) == 0xe ||
+ (CPUID_TO_FAMILY(cpu_info_primary.ci_signature) == 0xf &&
+ CPUID_TO_EXTMODEL(cpu_info_primary.ci_signature) < 0x4))) {
for (i = 0; x86_retpatch[i] != 0; i++) {
/* ret,nop,nop,ret -> lfence,ret */
patchbytes(x86_retpatch[i], 0x0f, 0xae, 0xe8);
Index: sys/arch/x86/x86/powernow.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/powernow.c,v
retrieving revision 1.7
diff -u -r1.7 powernow.c
--- sys/arch/x86/x86/powernow.c 27 Oct 2012 07:19:45 -0000 1.7
+++ sys/arch/x86/x86/powernow.c 13 Nov 2013 04:57:28 -0000
@@ -153,7 +153,7 @@
if (cpu_vendor != CPUVENDOR_AMD)
return 0;
- family = CPUID2FAMILY(ci->ci_signature);
+ family = CPUID_TO_BASEFAMILY(ci->ci_signature);
if (family != 0x06 && family != 0x0f)
return 0;
@@ -190,7 +190,7 @@
sc->sc_state = NULL;
sc->sc_freqs = NULL;
- family = CPUID2FAMILY(ci->ci_signature);
+ family = CPUID_TO_BASEFAMILY(ci->ci_signature);
switch (family) {
@@ -342,7 +342,7 @@
if (error || newp == NULL)
return error;
- family = CPUID2FAMILY(sc->sc_ci->ci_signature);
+ family = CPUID_TO_BASEFAMILY(sc->sc_ci->ci_signature);
if (rnode->sysctl_num == sc->sc_node_target && fq != oldfq) {
Index: sys/arch/x86/x86/tprof_amdpmi.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/tprof_amdpmi.c,v
retrieving revision 1.3
diff -u -r1.3 tprof_amdpmi.c
--- sys/arch/x86/x86/tprof_amdpmi.c 5 Feb 2011 14:04:40 -0000 1.3
+++ sys/arch/x86/x86/tprof_amdpmi.c 13 Nov 2013 04:57:28 -0000
@@ -178,8 +178,7 @@
uint64_t xc;
if (!(cpu_vendor == CPUVENDOR_AMD) ||
- CPUID2FAMILY(ci->ci_signature) +
- CPUID2EXTFAMILY(ci->ci_signature) != 0xf) { /* XXX */
+ CPUID_TO_FAMILY(ci->ci_signature) != 0xf) { /* XXX */
return ENOTSUP;
}
Index: sys/arch/x86/x86/tprof_pmi.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/tprof_pmi.c,v
retrieving revision 1.12
diff -u -r1.12 tprof_pmi.c
--- sys/arch/x86/x86/tprof_pmi.c 5 Feb 2011 14:04:40 -0000 1.12
+++ sys/arch/x86/x86/tprof_pmi.c 13 Nov 2013 04:57:28 -0000
@@ -227,7 +227,7 @@
uint64_t xc;
if (!(cpu_vendor == CPUVENDOR_INTEL &&
- CPUID2FAMILY(ci->ci_signature) == 15)) {
+ CPUID_TO_BASEFAMILY(ci->ci_signature) == 15)) {
return ENOTSUP;
}
Index: sys/arch/x86/x86/tsc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/tsc.c,v
retrieving revision 1.32
diff -u -r1.32 tsc.c
--- sys/arch/x86/x86/tsc.c 2 Jul 2013 00:01:17 -0000 1.32
+++ sys/arch/x86/x86/tsc.c 13 Nov 2013 04:57:28 -0000
@@ -95,17 +95,17 @@
* that it's safe on P-II and P-III Xeons due to the
* typical configuration of those systems.
*/
- switch (CPUID2FAMILY(ci->ci_signature)) {
+ switch (CPUID_TO_BASEFAMILY(ci->ci_signature)) {
case 0x05:
safe = true;
break;
case 0x06:
- safe = CPUID2MODEL(ci->ci_signature) == 0x0e ||
- CPUID2MODEL(ci->ci_signature) == 0x0f ||
- CPUID2MODEL(ci->ci_signature) == 0x0a;
+ safe = CPUID_TO_MODEL(ci->ci_signature) == 0x0e ||
+ CPUID_TO_MODEL(ci->ci_signature) == 0x0f ||
+ CPUID_TO_MODEL(ci->ci_signature) == 0x0a;
break;
case 0x0f:
- safe = CPUID2MODEL(ci->ci_signature) >= 0x03;
+ safe = CPUID_TO_MODEL(ci->ci_signature) >= 0x03;
break;
}
} else if (cpu_vendor == CPUVENDOR_AMD) {
@@ -118,7 +118,7 @@
* We're only going to follow the simple, reliable
* ones.
*/
- switch (CPUID2FAMILY(ci->ci_signature)) {
+ switch (CPUID_TO_BASEFAMILY(ci->ci_signature)) {
case 0x06:
case 0x07:
/*
Index: sys/arch/x86/x86/viac7temp.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/viac7temp.c,v
retrieving revision 1.6
diff -u -r1.6 viac7temp.c
--- sys/arch/x86/x86/viac7temp.c 20 Jun 2011 17:07:21 -0000 1.6
+++ sys/arch/x86/x86/viac7temp.c 13 Nov 2013 04:57:28 -0000
@@ -71,8 +71,8 @@
if (cpu_vendor != CPUVENDOR_IDT)
return 0;
- model = CPUID2MODEL(ci->ci_signature);
- family = CPUID2FAMILY(ci->ci_signature);
+ model = CPUID_TO_MODEL(ci->ci_signature);
+ family = CPUID_TO_FAMILY(ci->ci_signature);
if (family != 0x06 || model < 0x09)
return 0;
--
-----------------------------------------------
SAITOH Masanobu (msaitoh%execsw.org@localhost
msaitoh%netbsd.org@localhost)
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