Re: mips SOFTFLOAT status ?

[Manuel Bouyer <bouyer%antioche.eu.org@localhost>]

On Thu, Jan 28, 2010 at 09:25:33AM -0800, Matt Thomas wrote:
> > OK, it turns out that our processor model doesn't take a trap on all
> > FPU instructions ...
> > sorry for the noise.
> 
> You don't get a COP2 unavailable exception?

that would be COP1, isn't it ? 

> Wow.  What chip is this?

this one:
https://www-soc.lip6.fr/trac/tsar/

well, this chip doesn't really exist yet, but we a systemC model :)
We hope to have a working FPGA implementation by the end of the year.

-- 
Manuel Bouyer <bouyer%antioche.eu.org@localhost>
     NetBSD: 26 ans d'experience feront toujours la difference
--