Re: SGI MIPS, Speculative Execution issue

["Maciej W. Rozycki" <macro%orcam.me.uk@localhost>]

On Sat, 26 Oct 2024, DiTBho Down in The Bunny hole wrote:

> I mean, I know what coherence of the cache means in a multiprocessor
> environment, but I'm a bit confused by what I read for these mono
> processor systems.

 For UP it means that there is no bus snooping implemented in the CPU to 
support DMA bus masters.  Consequently DMA reads will supply data from RAM 
regardless if there's dirty data in the CPU's cache for the corresponding 
location and DMA writes will update data in RAM only regardless if there's 
corresponding data (dirty or clean) in the CPU's cache.

 So you need to synchronise RAM with the CPU's cache by hand via software 
means for the affected memory area ahead of any DMA transfer, normally by 
issuing write-back and invalidate requests for the relevant cache lines 
(the MIPS architecture has suitable CPU machine instructions for this 
purpose).

 In a cache-coherent system this is resolved transparently by hardware and
such synchronisation happens automatically.

 HTH,

  Maciej