Re: Is pmax alive?

[Felix Deichmann <m4j0rd0m0%gmail.com@localhost>]

2016-06-13 2:23 GMT+02:00 David Holland <dholland-mips%netbsd.org@localhost>:
> The problem I've always had is getting authoritative information about
> the requirements.
>
> That and (especially on early r3xxx and r4xxx models) some of them
> vary randomly from model to model.

You are probably not asking for the basics from Patterson and
Hennesy's academic standard work on this topic, right?

Is something like the "MIPS32 Architecture For Programmers" what you
are looking for?
(Then get it as long as it is still online! :))

http://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol1.pdf
http://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf
http://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol3.pdf

Volume 3, chapter 7 is about "CP0 hazards", seems to have such a
"canonical table" you asked for, although:

"Some MIPS implementations have placed the entire burden on the kernel
programmer to pad the instruction stream in such a way that the second
instruction is spaced far enough from the first that the effects of
the first are seen by the second. Other MIPS implementations have
added full hardware interlocks such that the kernel programmer need
not pad."

sounds like we would need the docs for each implementation (i. e. the
actual CPU implementation) to tell what to do exactly, as you already
mentioned?

Regards,
Felix