Re: IBM405GP/GPr OPB bus_space endian (powerpc/ibm4xx/dev/opb.c)

[Shigeyuki Fukushima <shige%netbsd.org@localhost>]

Hi,

Why my e-mail wasn't delivered via port-powerpc@? ;(

Simon Burge wrote:
>>>I wonder if it is possible to just attach the MI gpio directly to the
>>>opb with something like:
>>>     gpio* at opb? addr ? irq ?
>>>and
>>>     device  gpio: gpiobus
>>>     attach  gpio at opb with gpio_plb
>>>     file    arch/powerpc/ibm4xx/dev/gpio_opb.c      gpio
>>>and drop the intermediate gpio_opb/opbgpio/whatever device?
>>
>>It seems that this syntax is invalid.
>>/usr/src/sys/arch/powerpc/conf/files.ibm4xx:33: redifinition of `gpio'
>>/usr/src/sys/arch/powerpc/conf/files.ibm4xx:34: redifinition of `gpio'
>>/usr/src/sys/arch/evbppc/conf/OPENBLOCKS266:169: `gpio' cannot attach to
>> `opb'.
> Jared and Quentin (both CC'd here) have some ideas on directly attaching
> the gpio to the opb.  Jared set up the net4801 (i386) so that the gpio
> was directly attached to the PCI-ISA bridge.  I'll let them speak up
> about that.

Humm...
A GPIO controller has various functions by each chip.
Currently imported GPIO framework is a separate model between
controller-dependent devices(such as IBM4xx On-Chip GPIO on OPB) and
controller-independent devices (sys/dev/gpio).

This model is same as gpiic (I2C bus).
Please see sys/arch/powerpc/ibm4xx/dev/gpiic_opb.c.

OpneBlockS266 boot message is the following:
 :
opbgpio0 at opb0 addr 0xef600700: On-Chip GPIO controller
gpio0 at opbgpio0: 24 pins
gpiic0 at opb0 addr 0xef600500 irq 2: On-Chip IIC controller
iic0 at gpiic0: I2C bus
xrtc0 at iic0 addr 0x6f: Xicor X1226 Real-time Clock/NVRAM
 :

If we remove a glue device (such as opbgpio*, gpiic*),
we must essencialy refine OpenBSD GPIO framework, and I2C framework too.

> This I'm now totally confused about!  I'll have another look at it
> tomorrow.

Ok, please check it.

-- 
Kind Regards,
--- shige
Shigeyuki Fukushima <shige@{FreeBSD,jp.FreeBSD,NetBSD}.org>