-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, On May 25, 2008, at 05:20, Frank Wille wrote:
Tim Rightnour wrote:locore is entered with caches disabled, MMU disabled, BATs and SRs invalidated. MSR has only the IP-bit set.Anybody remembers a similar problem? Any idea what I could check or try?What kind of CPU is that exactly?A 233MHz 604e. No L2-cache present.some of the CPU's have a very specificset of operations you have to perform in a very specific order to turncaches on and off. Its usually documented in one of the CPU manuals.I'm reading the 604 User's Manual, but I didn't find examples for such asequence.BTW, I tried the same sequence to enable/invalidate caches on my Efika (5200B),which has caches already enabled in OF, and it crashed too!
Hmm, I have a kinda-sorta similar problem on ohare-based Macs with external L2 cache - if I enable it too late the machine goes bananas and ofb's cache trickery deadlocks it ( which is one of the motivations for switching to genfb )
have fun Michael -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.7 (Darwin) iQEVAwUBSDlji8pnzkX8Yg2nAQLO8Af+K44s3UclxYZGJg5+f3L/PK3HdRLit1rV 7IpTrrp1g5Kyw7AQ8qkYsXOgZvy8My89/pvlMuakxZa48o2ZQlQNRhwFhRoE8xV9 ku+ET7pwSWp0xsWrq50dOvZ5uzJMKF/ovMYxCtlnboVBi0yQEj65l6erAId4ENFi bi+1/qkW9s47sNvnX0xzBG308Bjf32VpKND/DOGToWts6pfoCIZRhm89sOx4V55E xuWUYIjN9JOLVsqnM7P7qiCJGPgJ5+nfGEE49qcKIvvvS0dwaq413Hp13sqLa07x ZWR1DOca27KR9kwrFhfiiR0/9WKT/gRG8sz7H4KJAK0X/KZ14VgVqg== =TRg8 -----END PGP SIGNATURE-----