Re: NetBSD hardclock overhead growth

[Felix Deichmann <m4j0rd0m0%gmail.com@localhost>]

Am 26.08.2015 um 20:57 schrieb Michael L. Hitch:
>    I've added some test to get some of the information from the registers.

It's also easy to obtain this info from the console (see below).

>    The first two were from one of my VLC systems and shows that it has
> all 8 banks of cache.  The second one was from another VLC and looks
> like one bank is missing on that.  A third VLC I wasn't able to boot
> from to look at.

On one of my KA660, fresh from power-on/reset:

>>>e pr$_ccr
  I 00000025 00000014

The cache is already enabled when the console becomes ready!

>>>d pr$_ccr 0
>>>d pr$_ccr 1
>>>e pr$_ccr
  I 00000025 00000011
>>>e/p 20150800
  P 20150800 41C0003F

It has only 6 banks enabled by the firmware.

The interesting part is this test:

>>>d/p 20150800 ff
>>>e/p 20150800
  P 20150800 41C000FF

The KA48 System Board Specification says that you can write all bank 
enable bits, but reading them back will only yield the factory-enabled 
("lasar [sic!] fused") ones set to 1.
On the KA660, it seems this is not the case (also implied by the 
statement that the firmware writes the bank enable bits).

I don't have the time today to test our code with its bank checks. 
Hopefully this works well enough, as we do not rely on the firmware 
alone (why?) to handle the cache.

Regards,
Felix