On 2023-12-26 17:15, Mouse wrote:
interrupt enable <6> Read/write. Cleared by processor[...]at IPL 14 (hex). That is, an interrupt is requested whenever the function {interrupt enable AND ready} changes from 0 to 1.I don't, however, see any language implying that the interrupt request is - or isn't - rescinded if DONE or IE is cleared before the interrupt is taken. I don't rescind them. simh does. NetBSD seems to tolerate either (not surprising).
Well, this whole thread started because you noted that NetBSD does in fact not tolerate your implementation under some circumstances...
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