[src/trunk]: src/sys/arch/arm/include Add scr inline

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/21c72ae1bd4d
branches:  trunk
changeset: 328262:21c72ae1bd4d
user:      matt <matt%NetBSD.org@localhost>
date:      Sat Mar 29 23:33:20 2014 +0000

description:
Add scr inline

diffstat:

 sys/arch/arm/include/armreg.h |  3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diffs (17 lines):

diff -r 702591343ffd -r 21c72ae1bd4d sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Sat Mar 29 23:32:41 2014 +0000
+++ b/sys/arch/arm/include/armreg.h     Sat Mar 29 23:33:20 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.94 2014/03/26 01:14:52 matt Exp $ */
+/*     $NetBSD: armreg.h,v 1.95 2014/03/29 23:33:20 matt Exp $ */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -902,6 +902,7 @@
 ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
+ARMREG_READ_INLINE(scr, "p15,0,%0,c1,c1,0") /* Secure Configuration Register */
 ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */
 /* cp15 c2 registers */
 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */