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[src/trunk]: src/sys/arch/arm/omap OMAP4/OMAP5 changes.
details: https://anonhg.NetBSD.org/src/rev/702591343ffd
branches: trunk
changeset: 328261:702591343ffd
user: matt <matt%NetBSD.org@localhost>
date: Sat Mar 29 23:32:41 2014 +0000
description:
OMAP4/OMAP5 changes.
diffstat:
sys/arch/arm/omap/omap2_reg.h | 55 ++++++++++-
sys/arch/arm/omap/omap3_ehci.c | 171 ++++++++++++++++++++++++++++++-----
sys/arch/arm/omap/omap3_sdhc.c | 6 +-
sys/arch/arm/omap/omap3_uhhreg.h | 60 ++++++++----
sys/arch/arm/omap/omap3_usbtllreg.h | 7 +-
5 files changed, 246 insertions(+), 53 deletions(-)
diffs (truncated from 500 to 300 lines):
diff -r 967e2f613a40 -r 702591343ffd sys/arch/arm/omap/omap2_reg.h
--- a/sys/arch/arm/omap/omap2_reg.h Sat Mar 29 22:45:31 2014 +0000
+++ b/sys/arch/arm/omap/omap2_reg.h Sat Mar 29 23:32:41 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.23 2013/06/20 05:27:31 matt Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.24 2014/03/29 23:32:41 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -363,6 +363,47 @@
#define TI_AM335X_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIVCHACK __BIT(5)
#define TI_AM335X_CM_DIV_M2_DPLL_MPU_DPLL_CLKOUT_DIV __BITS(4,0)
+#define OMAP4_CM_L3INIT_CORE 0x5300 /* OMAP2_CM_BASE */
+#define OMAP5_CM_L3INIT_CORE 0x5600 /* OMAP2_CM_BASE */
+#define OMAP4_CM_L3INIT_HSMMC1_CLKCTRL 0x0008
+#define OMAP4_CM_L3INIT_HSMMC2_CLKCTRL 0x0030
+#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL_DIV2 __BIT(25)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_CLKSEL __BIT(24)
+#define OMAP5_CM_L3INIT_HSMMC_CLKCTRL_OPTFCLKEN_32KHZ_CLK __BIT(8)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE __BITS(1,0)
+#define OMAP4_CM_L3INIT_HSMMC_CLKCTRL_MODELMODE_HW 2
+#define OMAP4_CM_L3INIT_HSI_CLKCTRL 0x0038
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL 0x0058
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P2 __BIT(25)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P1 __BIT(24)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_FUNC48M_CLK __BIT(15)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK __BIT(14)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P1_CLK __BIT(13)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK __BIT(12)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P1_CLK __BIT(11)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK __BIT(10)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK __BIT(9)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P1_CLK __BIT(8)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK __BIT(7)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK __BIT(6)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_MODULEMODE_HW 2
+#define OMAP4_CM_L3INIT_USB_OTG_HS_CLKCTRL 0x0060
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_CLKSEL_60M __BIT(24)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_XCLK __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL 0x0068
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK __BIT(10)
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK __BIT(9)
+#define OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH0_CLK __BIT(8)
+#define OMAP5_CM_L3INIT_SATA_CLKCTRL 0x0088
+#define OMAP5_CM_L3INIT_SATA_CLKCTRL_OPTFCLKEN_REF_CLK __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL 0x00F0
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_OPTFCLKEN_REFCLK960M __BIT(8)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE __BITS(1,0)
+#define OMAP5_CM_L3INIT_USB_OTG_SS_CLKCTRL_MODULEMODE_HW 1
+
/*
* Power Management registers base, offsets, and size
*/
@@ -763,8 +804,8 @@
#define OHCI1_BASE_OMAP3 0x48064400
#define EHCI1_BASE_OMAP3 0x48064800
-#define OHCI1_BASE_OMAP4 0x4A064800
-#define EHCI1_BASE_OMAP4 0x4A064C00
+#define OHCI1_BASE_OMAP4 0x4A064800 /* also OMAP5 */
+#define EHCI1_BASE_OMAP4 0x4A064C00 /* also OMAP5 */
/*
* SDRC
@@ -781,6 +822,7 @@
/*
* PL310 L2CC (44xx)
*/
+#define OMAP4_SCU_BASE 0x48240000
#define OMAP4_L2CC_BASE 0x48242000
#define OMAP4_L2CC_SIZE 0x00001000 /* 4KB */
@@ -788,6 +830,13 @@
#define AHCI1_BASE_OMAP5 0x4a140000
+/* These also apply to OMAP5 */
+#define OMAP4_WUGEN_BASE 0x48281000
+#define OMAP4_WKG_CONTROL_0 0x00000000
+#define OMAP4_WKG_CONTROL_1 0x00000400
+#define OMAP4_AUX_CORE_BOOT0 0x00000800
+#define OMAP4_AUX_CORE_BOOT1 0x00000804
+
#define OMAP5_PRM_FRAC_INCREMENTER_NUMERATOR 0x48243210
#define PRM_FRAC_INCR_NUM_ABE_LP_MODE __BITS(27,16)
#define PRM_FRAC_INCR_NUM_SYS_MODE __BITS(11,0)
diff -r 967e2f613a40 -r 702591343ffd sys/arch/arm/omap/omap3_ehci.c
--- a/sys/arch/arm/omap/omap3_ehci.c Sat Mar 29 22:45:31 2014 +0000
+++ b/sys/arch/arm/omap/omap3_ehci.c Sat Mar 29 23:32:41 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $ */
+/* $NetBSD: omap3_ehci.c,v 1.10 2014/03/29 23:32:41 matt Exp $ */
/*-
* Copyright (c) 2010-2012 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.9 2013/06/18 15:23:18 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.10 2014/03/29 23:32:41 matt Exp $");
#include "locators.h"
@@ -110,7 +110,7 @@
/* USBTLL module */
#ifdef OMAP_3XXX
#define USBTLL_BASE 0x48062000
-#elif defined(OMAP4)
+#elif defined(OMAP4) || defined(OMAP5)
#define USBTLL_BASE 0x4a062000
#endif
#define USBTLL_SIZE 0x1000
@@ -118,7 +118,7 @@
/* HS USB HOST module */
#ifdef OMAP_3XXX
#define UHH_BASE 0x48064000
-#elif defined(OMAP4)
+#elif defined(OMAP4) || defined(OMAP5)
#define UHH_BASE 0x4a064000
#endif
#define UHH_SIZE 0x1000
@@ -127,6 +127,57 @@
OMAP3_EHCI_PORT_MODE_NONE,
OMAP3_EHCI_PORT_MODE_PHY,
OMAP3_EHCI_PORT_MODE_TLL,
+ OMAP3_EHCI_PORT_MODE_HSIC,
+};
+
+static const uint32_t uhh_map[3][4] = {
+#if defined(OMAP4) || defined(OMAP5)
+ {
+ [OMAP3_EHCI_PORT_MODE_NONE] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P1_MODE),
+ [OMAP3_EHCI_PORT_MODE_PHY] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P1_MODE),
+ [OMAP3_EHCI_PORT_MODE_TLL] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P1_MODE),
+ [OMAP3_EHCI_PORT_MODE_HSIC] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P1_MODE),
+ }, {
+ [OMAP3_EHCI_PORT_MODE_NONE] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P2_MODE),
+ [OMAP3_EHCI_PORT_MODE_PHY] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P2_MODE),
+ [OMAP3_EHCI_PORT_MODE_TLL] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P2_MODE),
+ [OMAP3_EHCI_PORT_MODE_HSIC] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P2_MODE),
+ }, {
+ [OMAP3_EHCI_PORT_MODE_NONE] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P3_MODE),
+ [OMAP3_EHCI_PORT_MODE_PHY] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_ULPI_PHY, UHH_HOSTCONFIG_P3_MODE),
+ [OMAP3_EHCI_PORT_MODE_TLL] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_UTMI, UHH_HOSTCONFIG_P3_MODE),
+ [OMAP3_EHCI_PORT_MODE_HSIC] =
+ __SHIFTIN(UHH_HOSTCONFIG_PMODE_HSIC, UHH_HOSTCONFIG_P3_MODE),
+ }
+#else
+ {
+ [OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_PHY] = 0,
+ [OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P1_ULPI_BYPASS,
+ }, {
+ [OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_PHY] = 0,
+ [OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P2_ULPI_BYPASS,
+ }, {
+ [OMAP3_EHCI_PORT_MODE_NONE] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_PHY] = 0,
+ [OMAP3_EHCI_PORT_MODE_TLL] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
+ [OMAP3_EHCI_PORT_MODE_HSIC] = UHH_HOSTCONFIG_P3_ULPI_BYPASS,
+ },
+#endif
};
struct omap3_ehci_softc {
@@ -155,6 +206,9 @@
static void omap3_dpll5_init(struct omap3_ehci_softc *);
static void omap3_usbhost_init(struct omap3_ehci_softc *, int);
#endif
+#if defined(OMAP4) || defined(OMAP5)
+static void omap4_usbhost_init(struct omap3_ehci_softc *, int);
+#endif
static void usbtll_reset(struct omap3_ehci_softc *);
static void usbtll_power(struct omap3_ehci_softc *, bool);
static void usbtll_init(struct omap3_ehci_softc *, int);
@@ -297,7 +351,7 @@
if (obio->obio_addr == EHCI1_BASE_OMAP3)
return 1;
#endif
-#ifdef OMAP4
+#if defined(OMAP4) || defined(OMAP5)
if (obio->obio_addr == EHCI1_BASE_OMAP4)
return 1;
#endif
@@ -318,6 +372,14 @@
} else if (strcmp(s, "tll") == 0) {
mode = OMAP3_EHCI_PORT_MODE_TLL;
#endif
+#if defined(OMAP4) || defined(OMAP5)
+ } else if (strcmp(s, "hsic") == 0) {
+ mode = OMAP3_EHCI_PORT_MODE_HSIC;
+#endif
+ } else if (strcmp(s, "none") == 0) {
+ mode = OMAP3_EHCI_PORT_MODE_NONE;
+ } else {
+ panic("%s: unknown port mode %s", __func__, s);
}
}
@@ -415,6 +477,9 @@
omap3_usbhost_init(sc, 1);
#endif /* OMAP_3XXX */
+#if defined(OMAP4) || defined(OMAP5)
+ omap4_usbhost_init(sc, 1);
+#endif
sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
@@ -587,6 +652,40 @@
}
#endif /* OMAP_3XXX */
+#if defined(OMAP4) || defined(OMAP5)
+static void
+omap4_usbhost_init(struct omap3_ehci_softc *sc, int enable)
+{
+ bus_space_tag_t iot = sc->sc.iot;
+ bus_space_handle_t ioh;
+ uint32_t val;
+ int err __diagused;
+#ifdef OMAP5
+ bus_size_t off = OMAP5_CM_L3INIT_CORE;
+#elif defined(OMAP4)
+ bus_size_t off = OMAP4_CM_L3INIT_CORE;
+#endif
+
+ err = bus_space_map(iot, OMAP2_CM_BASE + off, 0x100, 0, &ioh);
+ KASSERT(err == 0);
+
+ val = bus_space_read_4(iot, ioh, OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL);
+ val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK
+ | OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK;
+ bus_space_write_4(iot, ioh, OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL, val);
+
+ val = bus_space_read_4(iot, ioh, OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL);
+ val |= OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK
+ | OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK;
+ bus_space_write_4(iot, ioh, OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL, val);
+
+ bus_space_unmap(iot, ioh, 0x100);
+}
+#endif /* OMAP4 || OMAP5 */
static void
usbtll_reset(struct omap3_ehci_softc *sc)
{
@@ -648,28 +747,48 @@
static void
uhh_power(struct omap3_ehci_softc *sc, bool on)
{
+ int retry = 5000;
+
uint32_t v;
- int retry = 5000;
+ v = UHH_READ4(sc, UHH_REVISION);
+ const int vers = UHH_REVISION_MAJOR(v);
if (on) {
v = UHH_READ4(sc, UHH_SYSCONFIG);
- v &= ~(UHH_SYSCONFIG_SIDLEMODE_MASK|UHH_SYSCONFIG_MIDLEMODE_MASK);
- v |= UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY;
- v |= UHH_SYSCONFIG_CLOCKACTIVITY;
- v |= UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE;
- v |= UHH_SYSCONFIG_ENAWAKEUP;
- v &= ~UHH_SYSCONFIG_AUTOIDLE;
+ if (vers >= UHH_REVISION_VERS2) {
+ v &= ~UHH4_SYSCONFIG_STANDBYMODE;
+ v |= UHH4_SYSCONFIG_STANDBYMODE_SMARTSTANDBY;
+ v &= ~UHH4_SYSCONFIG_SIDLEMODE;
+ v |= UHH4_SYSCONFIG_SIDLEMODE_SMARTIDLE;
+ } else {
+ v &= ~UHH3_SYSCONFIG_MIDLEMODE_MASK;
+ v |= UHH3_SYSCONFIG_MIDLEMODE_SMARTSTANDBY;
+ v &= ~UHH3_SYSCONFIG_SIDLEMODE_MASK;
+ v |= UHH3_SYSCONFIG_SIDLEMODE_SMARTIDLE;
+ v |= UHH3_SYSCONFIG_CLOCKACTIVITY;
+ v |= UHH3_SYSCONFIG_ENAWAKEUP;
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