[src/trunk]: src/sys/arch/mips/mips Only need KX/SX if _LP64 && MULTIPROCESSO...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b3f1e30406e3
branches:  trunk
changeset: 338716:b3f1e30406e3
user:      matt <matt%NetBSD.org@localhost>
date:      Fri Jun 05 19:58:01 2015 +0000

description:
Only need KX/SX if _LP64 && MULTIPROCESSOR since cpu_info's are always in KSEG0

diffstat:

 sys/arch/mips/mips/spl.S |  19 +++++--------------
 1 files changed, 5 insertions(+), 14 deletions(-)

diffs (62 lines):

diff -r fd008006a9b1 -r b3f1e30406e3 sys/arch/mips/mips/spl.S
--- a/sys/arch/mips/mips/spl.S  Fri Jun 05 16:44:56 2015 +0000
+++ b/sys/arch/mips/mips/spl.S  Fri Jun 05 19:58:01 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: spl.S,v 1.6 2015/06/05 16:16:18 matt Exp $     */
+/*     $NetBSD: spl.S,v 1.7 2015/06/05 19:58:01 matt Exp $     */
 
 /*-
  * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
 #include <mips/asm.h>
 #include <mips/cpuregs.h>
 
-RCSID("$NetBSD: spl.S,v 1.6 2015/06/05 16:16:18 matt Exp $")
+RCSID("$NetBSD: spl.S,v 1.7 2015/06/05 19:58:01 matt Exp $")
 
 #include "assym.h"
 
@@ -86,7 +86,7 @@
        or      v1, MIPS_INT_MASK               # enable all interrupts
        xor     a0, v1                          # disable ipl's masked bits
        DYNAMIC_STATUS_MASK(a0,v0)              # machine dependent masking
-#ifdef _LP64
+#if defined(_LP64) && MULTIPROCESSOR
        li      v1, MIPS3_SR_KX | MIPS3_SR_UX   # keep 64-bit addressing on
        mtc0    v1, MIPS_COP_0_STATUS           ## disable interrupts
 #else
@@ -143,12 +143,7 @@
        or      v1, MIPS_INT_MASK               # set all INT bits
        xor     v1, a1                          # clear any bits for this IPL
        DYNAMIC_STATUS_MASK(v1,t0)              # machine dependent masking
-#ifdef _LP64
-       li      v1, MIPS3_SR_KX | MIPS3_SR_UX   # keep 64-bit addressing on
-       mtc0    v1, MIPS_COP_0_STATUS           ## disable interrupts
-#else
        mtc0    zero, MIPS_COP_0_STATUS         ## disable interrupts
-#endif
        COP0_SYNC
        INT_S   a0, CPU_INFO_CPL(a3)            ## save IPL in cpu_info (KSEG0)
        mtc0    v1, MIPS_COP_0_STATUS           ## store back
@@ -176,19 +171,15 @@
 STATIC_LEAF(_splsw_spl0)
        INT_L   v1, _C_LABEL(ipl_sr_map) + 4*IPL_NONE
        PTR_L   a3, L_CPU(MIPS_CURLWP)
-       xor     v1, MIPS_INT_MASK | MIPS_SR_INT_IE # invert and or in IE
+       or      v1, MIPS_SR_INT_IE              # mask sure interrupts are on
+       xor     v1, MIPS_INT_MASK               # invert
        mtc0    zero, MIPS_COP_0_CAUSE          # clear SOFT_INT bits
        COP0_SYNC
        mfc0    a0, MIPS_COP_0_STATUS
        NOP_L                                   # load delay
        or      v0, a0, v1
        DYNAMIC_STATUS_MASK(v0,t0)              # machine dependent masking
-#ifdef _LP64
-       li      v1, MIPS3_SR_KX | MIPS3_SR_UX   # keep 64-bit addressing on
-       mtc0    v1, MIPS_COP_0_STATUS           ## disable interrupts
-#else
        mtc0    zero, MIPS_COP_0_STATUS         ## disable interrupts
-#endif
        COP0_SYNC
 #if IPL_NONE == 0
        INT_S   zero, CPU_INFO_CPL(a3)          ## set ipl to 0