[src/trunk]: src/sys/arch/arm Fix cache probing on Cortex. Add missing CORTE...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a17c75ca74bb
branches:  trunk
changeset: 755777:a17c75ca74bb
user:      matt <matt%NetBSD.org@localhost>
date:      Sat Jun 19 20:42:43 2010 +0000

description:
Fix cache probing on Cortex.  Add missing CORTEX dependency in cpu.c

diffstat:

 sys/arch/arm/arm/cpufunc.c    |  28 +++++++++++++++++++---------
 sys/arch/arm/arm32/cpu.c      |   6 ++++--
 sys/arch/arm/include/armreg.h |   4 ++--
 3 files changed, 25 insertions(+), 13 deletions(-)

diffs (108 lines):

diff -r 4545b1c6cec2 -r a17c75ca74bb sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Sat Jun 19 19:49:24 2010 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Sat Jun 19 20:42:43 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.96 2010/06/19 19:44:57 matt Exp $        */
+/*     $NetBSD: cpufunc.c,v 1.97 2010/06/19 20:42:43 matt Exp $        */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.96 2010/06/19 19:44:57 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.97 2010/06/19 20:42:43 matt Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
@@ -1203,27 +1203,37 @@
 
 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
        if (CPU_CT_FORMAT(ctype) == 4) { 
-               u_int csid1, csid2;
+               u_int csid0, csid1, csid2;
+
                isize = 1U << (CPU_CT4_ILINE(ctype) + 2);
                dsize = 1U << (CPU_CT4_DLINE(ctype) + 2);
 
-               csid1 = get_cachesize_cp15(CPU_CSSR_L1); /* select L1 cache values */
-               arm_pdcache_ways = CPU_CSID_ASSOC(csid1) + 1;
-               arm_pdcache_line_size = dsize << CPU_CSID_LEN(csid1);
+               csid0 = get_cachesize_cp15(CPU_CSSR_L1); /* select L1 dcache values */
+               arm_pdcache_ways = CPU_CSID_ASSOC(csid0) + 1;
+               arm_pdcache_line_size = dsize;
                arm_pdcache_size = arm_pdcache_line_size * arm_pdcache_ways;
-               arm_pdcache_size *= CPU_CSID_NUMSETS(csid1);
+               arm_pdcache_size *= (CPU_CSID_NUMSETS(csid0) + 1);
+               arm_cache_prefer_mask = PAGE_SIZE;
+
+               arm_dcache_align = arm_pdcache_line_size;
+
+               csid1 = get_cachesize_cp15(CPU_CSSR_L1|CPU_CSSR_InD); /* select L1 icache values */
+               arm_picache_ways = CPU_CSID_ASSOC(csid1) + 1;
+               arm_picache_line_size = isize;
+               arm_picache_size = arm_picache_line_size * arm_picache_ways;
+               arm_picache_size *= (CPU_CSID_NUMSETS(csid1) + 1);
                arm_cache_prefer_mask = PAGE_SIZE;
 
                arm_dcache_align = arm_pdcache_line_size;
 
                csid2 = get_cachesize_cp15(CPU_CSSR_L2); /* select L2 cache values */
                arm_dcache_l2_assoc = CPU_CSID_ASSOC(csid2) + 1;
-               arm_dcache_l2_linesize = dsize << CPU_CSID_LEN(csid2);
+               arm_dcache_l2_linesize = 1 << (CPU_CSID_LEN(csid2) + 2);
                arm_dcache_l2_nsets = CPU_CSID_NUMSETS(csid2) + 1;
                arm_pcache_type = CPU_CT_CTYPE_WB14;
                goto out;
        }
-#endif /* ARM_MMU_V6 > 0 */
+#endif /* ARM_MMU_V6 + ARM_MMU_V7 > 0 */
 
        if ((ctype & CPU_CT_S) == 0)
                arm_pcache_unified = 1;
diff -r 4545b1c6cec2 -r a17c75ca74bb sys/arch/arm/arm32/cpu.c
--- a/sys/arch/arm/arm32/cpu.c  Sat Jun 19 19:49:24 2010 +0000
+++ b/sys/arch/arm/arm32/cpu.c  Sat Jun 19 20:42:43 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.75 2010/06/19 19:49:24 matt Exp $    */
+/*     $NetBSD: cpu.c,v 1.76 2010/06/19 20:42:43 matt Exp $    */
 
 /*
  * Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
 
 #include <sys/param.h>
 
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.75 2010/06/19 19:49:24 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.76 2010/06/19 20:42:43 matt Exp $");
 
 #include <sys/systm.h>
 #include <sys/malloc.h>
@@ -623,6 +623,8 @@
 #endif
 #if defined(CPU_ARM11)
        case CPU_CLASS_ARM11J:
+#endif
+#if defined(CPU_CORTEX)
        case CPU_CLASS_CORTEX:
 #endif
 #if defined(CPU_FA526)
diff -r 4545b1c6cec2 -r a17c75ca74bb sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Sat Jun 19 19:49:24 2010 +0000
+++ b/sys/arch/arm/include/armreg.h     Sat Jun 19 20:42:43 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.43 2010/06/19 19:44:58 matt Exp $ */
+/*     $NetBSD: armreg.h,v 1.44 2010/06/19 20:42:43 matt Exp $ */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -346,7 +346,7 @@
 #define        CPU_CSID_CTYPE_WB       0x40000000      /* write-back avail */ 
 #define        CPU_CSID_CTYPE_RA       0x20000000      /* read-allocation avail */ 
 #define        CPU_CSID_CTYPE_WA       0x10000000      /* write-allocation avail */ 
-#define        CPU_CSID_NUMSETS(x)     (((x) >> 12) & 0xffff)
+#define        CPU_CSID_NUMSETS(x)     (((x) >> 13) & 0x7fff)
 #define        CPU_CSID_ASSOC(x)       (((x) >> 3) & 0x1ff)
 #define        CPU_CSID_LEN(x)         ((x) & 0x03)