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[src/trunk]: src/sys/arch Cleanup the armv7 changes. Add ARM_ARCH_7. Use C...



details:   https://anonhg.NetBSD.org/src/rev/4e93714d8604
branches:  trunk
changeset: 755774:4e93714d8604
user:      matt <matt%NetBSD.org@localhost>
date:      Sat Jun 19 19:44:57 2010 +0000

description:
Cleanup the armv7 changes.  Add ARM_ARCH_7.   Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well.  Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

diffstat:

 sys/arch/arm/arm/bus_space_asm_generic.S |   18 +-
 sys/arch/arm/arm/cpufunc.c               |   49 ++++----
 sys/arch/arm/arm/cpufunc_asm_armv6.S     |    4 +-
 sys/arch/arm/arm/cpufunc_asm_armv7.S     |  163 ++++++++++++++++--------------
 sys/arch/arm/arm32/cortex_pmc.c          |  149 ++++++++++++++++++++++++++++
 sys/arch/arm/arm32/cpu.c                 |   51 +++++---
 sys/arch/arm/arm32/locore.S              |   16 ++-
 sys/arch/arm/conf/files.arm              |   24 ++--
 sys/arch/arm/include/armreg.h            |   11 +-
 sys/arch/arm/include/cpuconf.h           |   17 ++-
 sys/arch/arm/include/cpufunc.h           |   11 +-
 sys/arch/arm/omap/omap2_mputmr.c         |    8 +-
 sys/arch/evbarm/conf/BEAGLEBOARD         |    6 +-
 sys/arch/evbarm/conf/TISDP2420           |    8 +-
 sys/arch/evbarm/conf/std.beagle          |    8 +-
 sys/arch/evbarm/conf/std.igepv2          |    6 +-
 16 files changed, 366 insertions(+), 183 deletions(-)

diffs (truncated from 1089 to 300 lines):

diff -r e93eb3ba8776 -r 4e93714d8604 sys/arch/arm/arm/bus_space_asm_generic.S
--- a/sys/arch/arm/arm/bus_space_asm_generic.S  Sat Jun 19 19:09:52 2010 +0000
+++ b/sys/arch/arm/arm/bus_space_asm_generic.S  Sat Jun 19 19:44:57 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bus_space_asm_generic.S,v 1.5 2005/12/11 12:16:41 christos Exp $       */
+/*     $NetBSD: bus_space_asm_generic.S,v 1.6 2010/06/19 19:44:57 matt Exp $   */
 
 /*
  * Copyright (c) 1997 Causality Limited.
@@ -49,7 +49,7 @@
        ldrb    r0, [r1, r2]
        mov     pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_r_2)
        ldrh    r0, [r1, r2]
        mov     pc, lr
@@ -67,7 +67,7 @@
        strb    r3, [r1, r2]
        mov     pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_w_2)
        strh    r3, [r1, r2]
        mov     pc, lr
@@ -95,7 +95,7 @@
 
        mov     pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_rm_2)
        add     r0, r1, r2
        mov     r1, r3
@@ -143,7 +143,7 @@
 
        mov     pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_wm_2)
        add     r0, r1, r2
        mov     r1, r3
@@ -191,7 +191,7 @@
 
        mov     pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_rr_2)
        add     r0, r1, r2
        mov     r1, r3
@@ -239,7 +239,7 @@
 
        mov     pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_wr_2)
        add     r0, r1, r2
        mov     r1, r3
@@ -286,7 +286,7 @@
 
        mov     pc, lr
 
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_sr_2)
        add     r0, r1, r2
        mov     r1, r3
@@ -318,7 +318,7 @@
  * copy region
  */
 
-#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) > 0
+#if (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7) > 0
 ENTRY(generic_armv4_bs_c_2)
        add     r0, r1, r2
        ldr     r2, [sp, #0]
diff -r e93eb3ba8776 -r 4e93714d8604 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Sat Jun 19 19:09:52 2010 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Sat Jun 19 19:44:57 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.95 2010/06/16 22:06:53 jmcneill Exp $    */
+/*     $NetBSD: cpufunc.c,v 1.96 2010/06/19 19:44:57 matt Exp $        */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.95 2010/06/16 22:06:53 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.96 2010/06/19 19:44:57 matt Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
@@ -1081,8 +1081,8 @@
 #endif
 /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
 
-#if defined(CPU_CORTEXA8)
-struct cpu_functions cortexa8_cpufuncs = {
+#if defined(CPU_CORTEX)
+struct cpu_functions cortex_cpufuncs = {
        /* CPU functions */
 
        .cf_id                  = cpufunc_id,
@@ -1139,7 +1139,7 @@
        .cf_setup               = armv7_setup
 
 };
-#endif /* CPU_CORTEXA8 */
+#endif /* CPU_CORTEX */
 
 
 /*
@@ -1155,7 +1155,7 @@
     defined(CPU_FA526) || \
     defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
-    defined(CPU_CORTEXA8)
+    defined(CPU_CORTEX)
 static void get_cachetype_cp15(void);
 
 /* Additional cache information local to this file.  Log2 of some of the
@@ -1170,10 +1170,10 @@
 {
     u_int csid;
 
-#if (CPU_CORTEXA8) > 0
+#if (CPU_CORTEX) > 0
+    __asm volatile(".arch\tarmv7a");
     __asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (cssr));
-    /* GAS does not have the ISB instruction ATM */
-    __asm volatile(".word 0xF57FF06F;"); /* sync to the new cssr */
+    __asm volatile("isb");     /* sync to the new cssr */
 #else
     __asm volatile("mcr p15, 1, %0, c0, c0, 2" :: "r" (cssr));
 #endif
@@ -1693,11 +1693,12 @@
                return 0;
        }
 #endif /* CPU_XSCALE_IXP425 */
-#if defined(CPU_CORTEXA8)
+#if defined(CPU_CORTEX)
        if (cputype == CPU_ID_CORTEXA8R1 ||
            cputype == CPU_ID_CORTEXA8R2 ||
-           cputype == CPU_ID_CORTEXA8R3) {
-               cpufuncs = cortexa8_cpufuncs;
+           cputype == CPU_ID_CORTEXA8R3 ||
+           cputype == CPU_ID_CORTEXA9R1) {
+               cpufuncs = cortex_cpufuncs;
                cpu_reset_needs_v4_MMU_disable = 1;     /* V4 or higher */
                cpu_do_powersave = 1;                   /* Enable powersave */
                get_cachetype_cp15();
@@ -1707,7 +1708,7 @@
 
                return 0;
        }
-#endif /* CPU_CORTEXA8 */
+#endif /* CPU_CORTEX */
        /*
         * Bzzzz. And the answer was ...
         */
@@ -2094,7 +2095,7 @@
        defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
        defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
        defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARM1136) || \
-       defined(CPU_FA526) || defined(CPU_CORTEXA8)
+       defined(CPU_FA526) || defined(CPU_CORTEX)
 
 #define IGN    0
 #define OR     1
@@ -2546,7 +2547,7 @@
 }
 #endif /* CPU_ARM11 */
 
-#if defined(CPU_CORTEXA8)
+#if defined(CPU_CORTEX)
 struct cpu_option armv7_options[] = {
     { "cpu.cache",      BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
     { "cpu.nocache",    OR,  BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
@@ -2629,18 +2630,20 @@
 
                        for (way = ways; way >= 0; way--) {
                                /* Clean by set/way */
-                               u_int sw = (way << wayshift) | (nsets << setshift) |
-                                       (level << 1);
-
-                               __asm volatile("mcr\tp15, 0, %0, c7, c10, 2" :: "r"(sw));
+                               const u_int sw = (way << wayshift)
+                                   | (nsets << setshift)
+                                   | (level << 1);
+
+                               __asm volatile("mcr\tp15, 0, %0, c7, c10, 2"
+                                   :: "r"(sw));
                        }
                }
        }
 
-       __asm volatile("mcr\tp15, 0, r0, c7, c10, 4"); /* DSB */
-       __asm volatile(".word 0xF57FF06F;");           /* ISB */
+       __asm volatile("dsb");
+       __asm volatile("isb");
 }
-#endif /* CPU_CORTEXA8 */
+#endif /* CPU_CORTEX */
 
 
 
@@ -2965,7 +2968,7 @@
 #endif /* CPU_IXP12X0 */
 
 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
-    defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || defined(CPU_CORTEXA8)
+    defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || defined(CPU_CORTEX)
 struct cpu_option xscale_options[] = {
 #ifdef COMPAT_12
        { "branchpredict",      BIC, OR,  CPU_CONTROL_BPRD_ENABLE },
diff -r e93eb3ba8776 -r 4e93714d8604 sys/arch/arm/arm/cpufunc_asm_armv6.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv6.S      Sat Jun 19 19:09:52 2010 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv6.S      Sat Jun 19 19:44:57 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_armv6.S,v 1.2 2008/04/27 18:58:43 matt Exp $       */
+/*     $NetBSD: cpufunc_asm_armv6.S,v 1.3 2010/06/19 19:44:57 matt Exp $       */
 
 /*
  * Copyright (c) 2002, 2005 ARM Limited
@@ -38,6 +38,8 @@
 #include <machine/cpu.h>
 #include <machine/asm.h>
 
+       .arch   armv6
+
 /*
  * Functions to set the MMU Translation Table Base register
  *
diff -r e93eb3ba8776 -r 4e93714d8604 sys/arch/arm/arm/cpufunc_asm_armv7.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S      Sat Jun 19 19:09:52 2010 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S      Sat Jun 19 19:44:57 2010 +0000
@@ -31,128 +31,137 @@
 #include <machine/cpu.h>
 #include <machine/asm.h>
 
-#define ISB .word 0xF57FF06F;
-#define DMB .word 0xF57FF05F;
-#define DSB .word 0xF57FF04F;
-#define WFI .word 0xC320F003;
+#define entrysize              #32
 
-#define DCACHE_SIZE            0x00008000
-
-#define entrysize              #32
+       .arch   armv7a
 
 
 ENTRY(armv7_cpu_sleep)
-    tst r0, #0x00000000                        @shouldn't sleep 0
-    WFI 
-    RET
+       tst     r0, #0x00000000         @shouldn't sleep 0
+       wfi
+       RET
+END(armv7_cpu_sleep)
 
 ENTRY(armv7_wait)
-    mrc p15, 0, r0, c2, c0, 0  /* arbitrary read of CP15 */
-    add r0, r0, #0                        /* a stall */
-    RET
+       mrc     p15, 0, r0, c2, c0, 0   @arbitrary read of CP15
+       add     r0, r0, #0              @a stall
+       RET
+END(armv7_wait)
 
 ENTRY(armv7_context_switch)
-    mcr p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-    mcr p15, 0, r0, c2, c0, 0  /* set the new TTB */
-    mcr p15, 0, r0, c8, c7, 0  /* flush the I+D */
-    RET
+       mcr     p15, 0, r0, c7, c10, 4  @drain the write buffer
+       mcr     p15, 0, r0, c2, c0, 0   @set the new TTB
+       mcr     p15, 0, r0, c8, c7, 0   @flush the I+D
+       RET
+END(armv7_context_switch)
 
 ENTRY(armv7_tlb_flushID_SE)
-    mcr p15, 0, r0, c8, c7, 1  /* flush I+D tlb single entry */
-    mcr p15, 0, r0, c7, c10, 4  /* drain write buffer */
-    RET
+       mcr     p15, 0, r0, c8, c7, 1   @flush I+D tlb single entry
+       mcr     p15, 0, r0, c7, c10, 4  @drain write buffer
+       RET
+END(armv7_tlb_flushID_SE)
 
 
 ENTRY(armv7_setttb)
 /* Does this even exist on armv7? */



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