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[src/trunk]: src/sys/arch Don't use an asm in pmap_activate to update the TTB...
details: https://anonhg.NetBSD.org/src/rev/b0fec6b09309
branches: trunk
changeset: 781671:b0fec6b09309
user: matt <matt%NetBSD.org@localhost>
date: Sat Sep 22 00:33:36 2012 +0000
description:
Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).
With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.
diffstat:
sys/arch/acorn32/acorn32/rpc_machdep.c | 6 +-
sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c | 6 +-
sys/arch/arm/arm/cpufunc_asm_arm11.S | 11 +-
sys/arch/arm/arm/cpufunc_asm_arm11x6.S | 16 ++--
sys/arch/arm/arm/cpufunc_asm_arm67.S | 14 ++-
sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S | 13 ++-
sys/arch/arm/arm/cpufunc_asm_arm8.S | 15 ++-
sys/arch/arm/arm/cpufunc_asm_arm9.S | 12 ++-
sys/arch/arm/arm/cpufunc_asm_armv5.S | 11 ++-
sys/arch/arm/arm/cpufunc_asm_armv5_ec.S | 11 ++-
sys/arch/arm/arm/cpufunc_asm_armv6.S | 11 +-
sys/arch/arm/arm/cpufunc_asm_armv7.S | 17 +++-
sys/arch/arm/arm/cpufunc_asm_fa526.S | 18 ++--
sys/arch/arm/arm/cpufunc_asm_sa1.S | 21 +++--
sys/arch/arm/arm/cpufunc_asm_xscale.S | 18 +++-
sys/arch/arm/arm32/arm32_kvminit.c | 8 +-
sys/arch/arm/arm32/cpu.c | 83 +++++------------------
sys/arch/arm/arm32/pmap.c | 27 ++++++-
sys/arch/arm/cortex/pl310.c | 28 +++----
sys/arch/arm/include/arm32/pmap.h | 19 +----
sys/arch/arm/include/armreg.h | 8 ++-
sys/arch/arm/include/cpufunc.h | 30 ++++----
sys/arch/cats/cats/cats_machdep.c | 6 +-
sys/arch/evbarm/adi_brh/brh_machdep.c | 6 +-
sys/arch/evbarm/armadillo/armadillo9_machdep.c | 6 +-
sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c | 4 +-
sys/arch/evbarm/gemini/gemini_machdep.c | 6 +-
sys/arch/evbarm/gumstix/gumstix_machdep.c | 4 +-
sys/arch/evbarm/hdl_g/hdlg_machdep.c | 6 +-
sys/arch/evbarm/imx31/imx31lk_machdep.c | 6 +-
sys/arch/evbarm/integrator/integrator_machdep.c | 6 +-
sys/arch/evbarm/iq80310/iq80310_machdep.c | 6 +-
sys/arch/evbarm/iq80321/iq80321_machdep.c | 6 +-
sys/arch/evbarm/ixdp425/ixdp425_machdep.c | 6 +-
sys/arch/evbarm/ixm1200/ixm1200_machdep.c | 6 +-
sys/arch/evbarm/lubbock/lubbock_machdep.c | 6 +-
sys/arch/evbarm/mini2440/mini2440_machdep.c | 4 +-
sys/arch/evbarm/netwalker/netwalker_machdep.c | 6 +-
sys/arch/evbarm/npwr_fc/npwr_fc_machdep.c | 6 +-
sys/arch/evbarm/nslu2/nslu2_machdep.c | 6 +-
sys/arch/evbarm/osk5912/osk5912_machdep.c | 6 +-
sys/arch/evbarm/smdk2xx0/smdk2410_machdep.c | 6 +-
sys/arch/evbarm/smdk2xx0/smdk2800_machdep.c | 6 +-
sys/arch/evbarm/tisdp24xx/sdp24xx_machdep.c | 6 +-
sys/arch/evbarm/tsarm/tsarm_machdep.c | 6 +-
sys/arch/evbarm/viper/viper_machdep.c | 6 +-
sys/arch/hpcarm/hpcarm/pxa2x0_hpc_machdep.c | 6 +-
sys/arch/hpcarm/hpcarm/sa11x0_hpc_machdep.c | 6 +-
sys/arch/iyonix/iyonix/iyonix_machdep.c | 6 +-
sys/arch/netwinder/netwinder/netwinder_machdep.c | 6 +-
sys/arch/shark/ofw/ofw.c | 6 +-
sys/arch/zaurus/zaurus/machdep.c | 6 +-
52 files changed, 290 insertions(+), 287 deletions(-)
diffs (truncated from 1821 to 300 lines):
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/acorn32/acorn32/rpc_machdep.c
--- a/sys/arch/acorn32/acorn32/rpc_machdep.c Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/acorn32/acorn32/rpc_machdep.c Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rpc_machdep.c,v 1.85 2012/08/16 18:22:37 matt Exp $ */
+/* $NetBSD: rpc_machdep.c,v 1.86 2012/09/22 00:33:36 matt Exp $ */
/*
* Copyright (c) 2000-2002 Reinoud Zandijk.
@@ -55,7 +55,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: rpc_machdep.c,v 1.85 2012/08/16 18:22:37 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rpc_machdep.c,v 1.86 2012/09/22 00:33:36 matt Exp $");
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -798,7 +798,7 @@
printf("switching to new L1 page table\n");
#endif
- cpu_setttb(kernel_l1pt.pv_pa);
+ cpu_setttb(kernel_l1pt.pv_pa, true);
/*
* We must now clean the cache again....
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c
--- a/sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: eb7500atx_machdep.c,v 1.24 2012/08/16 18:22:38 matt Exp $ */
+/* $NetBSD: eb7500atx_machdep.c,v 1.25 2012/09/22 00:33:37 matt Exp $ */
/*
* Copyright (c) 2000-2002 Reinoud Zandijk.
@@ -55,7 +55,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: eb7500atx_machdep.c,v 1.24 2012/08/16 18:22:38 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: eb7500atx_machdep.c,v 1.25 2012/09/22 00:33:37 matt Exp $");
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -742,7 +742,7 @@
#ifdef VERBOSE_INIT_ARM
printf("switching to new L1 page table\n");
#endif
- cpu_setttb(kernel_l1pt.pv_pa);
+ cpu_setttb(kernel_l1pt.pv_pa, true);
/*
* We must now clean the cache again....
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/arm/arm/cpufunc_asm_arm11.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm11.S Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm11.S Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm11.S,v 1.8 2012/07/18 20:09:19 skrll Exp $ */
+/* $NetBSD: cpufunc_asm_arm11.S,v 1.9 2012/09/22 00:33:37 matt Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@@ -46,15 +46,14 @@
*/
ENTRY(arm11_setttb)
#ifdef PMAP_CACHE_VIVT
- stmfd sp!, {r0, lr}
- bl _C_LABEL(armv6_idcache_wbinv_all)
- ldmfd sp!, {r0, lr}
+#error arm11 does not have a VIVT cache.
#endif
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ cmp r1, #0
+ mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+ mcrne p15, 0, r0, c7, c10, 4 /* drain write buffer */
RET
/*
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/arm/arm/cpufunc_asm_arm11x6.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm11x6.S Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm11x6.S Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.1 2012/07/21 12:19:15 skrll Exp $ */
+/* $NetBSD: cpufunc_asm_arm11x6.S,v 1.2 2012/09/22 00:33:37 matt Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -63,7 +63,7 @@
#include <machine/cpu.h>
#include <machine/asm.h>
-RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.1 2012/07/21 12:19:15 skrll Exp $")
+RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.2 2012/09/22 00:33:37 matt Exp $")
#if 0
#define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -116,14 +116,16 @@
ENTRY(arm11x6_setttb)
#ifdef PMAP_CACHE_VIVT
- Flush_D_cache(r1)
- Invalidate_I_cache(r1, r2)
+ Flush_D_cache(r2)
+ Invalidate_I_cache(r2, r3)
#else
- mov r1, #0
+ mov r2, #0
#endif
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
- mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
- mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */
+
+ cmp r1, #0
+ mcrne p15, 0, r2, c8, c7, 0 /* invalidate I+D TLBs */
+ mcrne p15, 0, r2, c7, c10, 4 /* drain write buffer */
RET
ENTRY_NP(arm11x6_idcache_wbinv_all)
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/arm/arm/cpufunc_asm_arm67.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm67.S Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm67.S Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm67.S,v 1.4 2010/01/03 04:25:16 uebayasi Exp $ */
+/* $NetBSD: cpufunc_asm_arm67.S,v 1.5 2012/09/22 00:33:37 matt Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@@ -45,22 +45,26 @@
* addresses that are about to change.
*/
ENTRY(arm67_setttb)
- mcr p15, 0, r0, c7, c0, 0
+ cmp r1, #0
+
+ /* wbinv entire L1 I$ and D$ caches */
+ movne r2, #0
+ mcrne p15, 0, r2, c7, c0, 0
/* Write the TTB */
mcr p15, 0, r0, c2, c0, 0
/* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c5, c0, 0
+ mcrne p15, 0, r0, c5, c0, 0
/* For good measure we will flush the IDC as well */
- mcr p15, 0, r0, c7, c0, 0
+ mcrne p15, 0, r0, c7, c0, 0
/* Make sure that pipeline is emptied */
mov r0, r0
mov r0, r0
- mov pc, lr
+ RET
/*
* TLB functions
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.4 2010/01/03 04:25:16 uebayasi Exp $ */
+/* $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.5 2012/09/22 00:33:37 matt Exp $ */
/*
* Copyright (c) 2001 John Fremlin
@@ -44,21 +44,26 @@
* addresses that are about to change.
*/
ENTRY(arm7tdmi_setttb)
+ mov r3, lr /* ditto with lr */
+ mov r2, r1 /* store the flush flag in a safe place */
mov r1, r0 /* store the TTB in a safe place */
- mov r2, lr /* ditto with lr */
- bl _C_LABEL(arm7tdmi_cache_flushID)
+ cmp r2, #0
+ blne _C_LABEL(arm7tdmi_cache_flushID)
/* Write the TTB */
mcr p15, 0, r1, c2, c0, 0
+ cmp r2, #0 @ do we need to flush
+ moveq pc, r3 @ if not, return
+
/* If we have updated the TTB we must flush the TLB */
bl _C_LABEL(arm7tdmi_tlb_flushID)
/* For good measure we will flush the IDC as well */
bl _C_LABEL(arm7tdmi_cache_flushID)
- mov pc, r2
+ mov pc, r3
/*
* TLB functions
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/arm/arm/cpufunc_asm_arm8.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm8.S Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm8.S Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm8.S,v 1.6 2010/01/03 04:25:16 uebayasi Exp $ */
+/* $NetBSD: cpufunc_asm_arm8.S,v 1.7 2012/09/22 00:33:37 matt Exp $ */
/*
* Copyright (c) 1997 ARM Limited
@@ -66,22 +66,25 @@
*/
ENTRY(arm8_setttb)
mrs r3, cpsr_all
- orr r1, r3, #(I32_bit | F32_bit)
- msr cpsr_all, r1
+ orr r2, r3, #(I32_bit | F32_bit)
+ msr cpsr_all, r2
stmfd sp!, {r0-r3, lr}
bl _C_LABEL(arm8_cache_cleanID)
ldmfd sp!, {r0-r3, lr}
- mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
+
+ cmp r1, #0 @ do we need to flush the caches?
+
+ mcrne p15, 0, r0, c7, c7, 0 /* flush I+D cache */
/* Write the TTB */
mcr p15, 0, r0, c2, c0, 0
/* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c8, c7, 0
+ mcrne p15, 0, r0, c8, c7, 0
/* For good measure we will flush the IDC as well */
- mcr p15, 0, r0, c7, c7, 0
+ mcrne p15, 0, r0, c7, c7, 0
/* Make sure that pipeline is emptied */
mov r0, r0
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/arm/arm/cpufunc_asm_arm9.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm9.S Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm9.S Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm9.S,v 1.8 2012/09/07 11:48:59 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm9.S,v 1.9 2012/09/22 00:33:37 matt Exp $ */
/*
* Copyright (c) 2001, 2004 ARM Limited
@@ -43,14 +43,18 @@
* addresses that are about to change.
*/
ENTRY(arm9_setttb)
+ cmp r1, #0
+ beq 1f
+
stmfd sp!, {r0, lr}
bl _C_LABEL(arm9_idcache_wbinv_all)
ldmfd sp!, {r0, lr}
-
+ cmp r0, #1 /* make sure EQ=0 */
+1:
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
- mov pc, lr
+ mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+ RET
/*
* TLB functions
diff -r 89d6fc372998 -r b0fec6b09309 sys/arch/arm/arm/cpufunc_asm_armv5.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv5.S Fri Sep 21 22:12:35 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv5.S Sat Sep 22 00:33:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_armv5.S,v 1.4 2012/09/07 11:48:59 matt Exp $ */
+/* $NetBSD: cpufunc_asm_armv5.S,v 1.5 2012/09/22 00:33:37 matt Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@@ -45,13 +45,16 @@
* addresses that are about to change.
*/
ENTRY(armv5_setttb)
+ cmp r1, #0
+ beq 1f
+
stmfd sp!, {r0, lr}
bl _C_LABEL(armv5_idcache_wbinv_all)
ldmfd sp!, {r0, lr}
+ cmp r0, #1
- mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
-
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+1: mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
+ mcrne p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
RET
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