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[src/trunk]: src/sys/arch/arm Before testing for VFP, make sure CP10 is enabl...
details: https://anonhg.NetBSD.org/src/rev/fef09f3d3eed
branches: trunk
changeset: 781672:fef09f3d3eed
user: matt <matt%NetBSD.org@localhost>
date: Sat Sep 22 01:44:12 2012 +0000
description:
Before testing for VFP, make sure CP10 is enabled. (And CP11 for Neon too).
diffstat:
sys/arch/arm/include/armreg.h | 5 ++++-
sys/arch/arm/include/vfpreg.h | 4 +++-
sys/arch/arm/vfp/vfp_init.c | 24 ++++++++++++++++++++++--
3 files changed, 29 insertions(+), 4 deletions(-)
diffs (96 lines):
diff -r b0fec6b09309 -r fef09f3d3eed sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h Sat Sep 22 00:33:36 2012 +0000
+++ b/sys/arch/arm/include/armreg.h Sat Sep 22 01:44:12 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.66 2012/09/22 00:33:37 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.67 2012/09/22 01:44:12 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -569,6 +569,9 @@
ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
+/* c1 registers */
+ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Register */
+ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Register */
/* c2 registers */
ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
diff -r b0fec6b09309 -r fef09f3d3eed sys/arch/arm/include/vfpreg.h
--- a/sys/arch/arm/include/vfpreg.h Sat Sep 22 00:33:36 2012 +0000
+++ b/sys/arch/arm/include/vfpreg.h Sat Sep 22 01:44:12 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vfpreg.h,v 1.4 2012/08/16 07:24:25 matt Exp $ */
+/* $NetBSD: vfpreg.h,v 1.5 2012/09/22 01:44:12 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -48,6 +48,7 @@
#define VFP_FPSID_PART_MSK 0x0000ff00 /* Part number */
#define VFP_FPSID_PART_VFP10 0x00001000 /* VFP10 */
#define VFP_FPSID_PART_VFP11 0x00002000 /* VFP11 */
+#define VFP_FPSID_PART_VFP30 0x00003000 /* VFP30 */
#define VFP_FPSID_VAR_MSK 0x000000f0 /* Variant */
#define VFP_FPSID_VAR_ARM10 0x000000a0 /* Variant ARM10 */
#define VFP_FPSID_VAR_ARM11 0x000000b0 /* Variant ARM11 */
@@ -55,6 +56,7 @@
#define FPU_VFP10_ARM10E 0x410001a0 /* Really a VFPv2 part */
#define FPU_VFP11_ARM11 0x410120b0
+#define FPU_VFP30_CORTEXA9 0x41033090
#define VFP_FPEXC_EX 0x80000000 /* Exception status bit */
#define VFP_FPEXC_EN 0x40000000 /* VFP Enable bit */
diff -r b0fec6b09309 -r fef09f3d3eed sys/arch/arm/vfp/vfp_init.c
--- a/sys/arch/arm/vfp/vfp_init.c Sat Sep 22 00:33:36 2012 +0000
+++ b/sys/arch/arm/vfp/vfp_init.c Sat Sep 22 01:44:12 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vfp_init.c,v 1.5 2012/08/16 18:16:25 matt Exp $ */
+/* $NetBSD: vfp_init.c,v 1.6 2012/09/22 01:44:12 matt Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -222,6 +222,23 @@
undefined_test = 0;
+#ifdef FPU_VFP
+ uint32_t cpacr = armreg_cpacr_read();
+ cpacr &= ~__BITS(21,20);
+ cpacr &= ~__BITS(23,22);
+
+ cpacr |= __SHIFTIN(1, __BITS(21,20));
+ cpacr |= __SHIFTIN(1, __BITS(23,22));
+ armreg_cpacr_write(cpacr);
+ cpacr = armreg_cpacr_read();
+ if ((cpacr & __BITS(23,22)) == 0) {
+ aprint_normal_dev(ci->ci_dev, "NEON not present\n");
+ }
+ if ((cpacr & __BITS(21,20)) == 0) {
+ aprint_normal_dev(ci->ci_dev, "VFP not present\n");
+ }
+#endif
+
const uint32_t fpsid = read_fpsid();
remove_coproc_handler(uh);
@@ -241,6 +258,9 @@
case FPU_VFP11_ARM11:
model = "VFP11";
break;
+ case FPU_VFP30_CORTEXA9:
+ model = "NEON MPE w/ VFP 3.0";
+ break;
default:
aprint_normal_dev(ci->ci_dev, "unrecognized VFP version %x\n",
fpsid);
@@ -250,7 +270,7 @@
if (fpsid != 0) {
aprint_normal("vfp%d at %s: %s\n",
- curcpu()->ci_dev->dv_unit, curcpu()->ci_dev->dv_xname,
+ device_unit(curcpu()->ci_dev), device_xname(curcpu()->ci_dev),
model);
}
evcnt_attach_dynamic(&vfpevent_use, EVCNT_TYPE_MISC, NULL,
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