[src/trunk]: src/common/lib/libc/arch x86: Add a note on membar_sync and mfence.

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9a7a1de4b136
branches:  trunk
changeset: 364728:9a7a1de4b136
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Sat Apr 09 12:07:29 2022 +0000

description:
x86: Add a note on membar_sync and mfence.

diffstat:

 common/lib/libc/arch/i386/atomic/atomic.S   |  8 +++++++-
 common/lib/libc/arch/x86_64/atomic/atomic.S |  8 +++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diffs (44 lines):

diff -r 5b71fbbddd34 -r 9a7a1de4b136 common/lib/libc/arch/i386/atomic/atomic.S
--- a/common/lib/libc/arch/i386/atomic/atomic.S Sat Apr 09 12:07:17 2022 +0000
+++ b/common/lib/libc/arch/i386/atomic/atomic.S Sat Apr 09 12:07:29 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: atomic.S,v 1.32 2022/04/09 12:07:17 riastradh Exp $    */
+/*     $NetBSD: atomic.S,v 1.33 2022/04/09 12:07:29 riastradh Exp $    */
 
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -197,6 +197,12 @@
 END(_membar_producer)
 
 ENTRY(_membar_sync)
+       /*
+        * MFENCE, or a serializing instruction like a locked addq,
+        * is necessary to order store-before-load.  Every other
+        * ordering -- load-before-anything, anything-before-store --
+        * is already guaranteed without explicit barriers.
+        */
        HOTPATCH_SSE2_MFENCE
        /* 7 bytes of instructions */
        LOCK
diff -r 5b71fbbddd34 -r 9a7a1de4b136 common/lib/libc/arch/x86_64/atomic/atomic.S
--- a/common/lib/libc/arch/x86_64/atomic/atomic.S       Sat Apr 09 12:07:17 2022 +0000
+++ b/common/lib/libc/arch/x86_64/atomic/atomic.S       Sat Apr 09 12:07:29 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: atomic.S,v 1.25 2022/04/09 12:07:17 riastradh Exp $    */
+/*     $NetBSD: atomic.S,v 1.26 2022/04/09 12:07:29 riastradh Exp $    */
 
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -272,6 +272,12 @@
 END(_membar_producer)
 
 ENTRY(_membar_sync)
+       /*
+        * MFENCE, or a serializing instruction like a locked addq,
+        * is necessary to order store-before-load.  Every other
+        * ordering -- load-before-anything, anything-before-store --
+        * is already guaranteed without explicit barriers.
+        */
        HOTPATCH_SSE2_MFENCE
        /* 8 bytes of instructions */
        LOCK