Re: NetBSD hardclock overhead growth

["Michael L. Hitch" <mhitch%NetBSD.org@localhost>]

On Thu, 27 Aug 2015, Michael L. Hitch wrote:

>  I figured there should be a way to do that.
>
> > > > > e pr$_ccr
> >  I 00000025 00000014
>
>  I couldn't remember how to modify/examine the registers.  Thanks, now I can 
> check my other VLC.

  Didn't work on the VLC,

  But after a little searching:

> > > e/i 25
  I 00000025 00000010

> > > d/i 25 11

> > > e/i 25
  I 00000025 00000011

> > > e/p 20150800
  P 20150800 000000F7

> > > d/p 20150800 ff

> > > e/p 20150800
  P 20150800 000000F7

> > The KA48 System Board Specification says that you can write all bank enable 
> > bits, but reading them back will only yield the factory-enabled ("lasar 
> > [sic!] fused") ones set to 1.
> > On the KA660, it seems this is not the case (also implied by the statement 
> > that the firmware writes the bank enable bits).
>
>  I'll try this on my second VLC, which showed one bank missing.

  Looks like the Specification is correct.

  This also allows testing how well the cache peforms.  Since we don't 
currently change BEHM, I can disable all the banks.

  Zero banks enabled:
Microseconds for one run through Dhrystone:  469.8
Dhrystones per Second:                      2128.6

  One bank enabled:
Microseconds for one run through Dhrystone:  169.9
Dhrystones per Second:                      5885.8

  Three banks enabled:
Microseconds for one run through Dhrystone:   99.9
Dhrystones per Second:                      10010.0

  Seven banks enabled:
Microseconds for one run through Dhrystone:   89.9
Dhrystones per Second:                      11123.5

  Dhrystone is probably small enough it fits in 3 (or maybe even 2) banks.

  With no cache banks enable, it runs about the same as John was seeing.

Mike

---
Michael L. Hitch                        mhitch%montana.edu@localhost
Operations Consulting,  Information Technology Center
Montana State University, Bozeman, MT     USA